AM335x GPMC read/write data to nand from application

/*
Test file for talking to external memory using GPMC pins in GPMC mode.
*/

#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>
#include <fcntl.h>
#include <sys/mman.h>
#include "hw_gpmc.h" // SYS-BIOS
#include "hw_cm_per.h" // SYS-BIOS
#include "soc_AM335x.h" // SYS-BIOS

#define MMAP_OFFSET 0x44c00000

// redefine HWREG macro to use MMAP result
#define HWREG(x) __mmapl[(x-MMAP_OFFSET)/4]
#define GPMCREG(x) __mmapl[(x-MMAP_OFFSET + SOC_GPMC_0_REGS )/4]

#define CSC_FPGA

volatile uint32_t *__mmapl;

void gpmc_init_cs(int csNum, int burst_en, int base)
{
    uint16_t clk_divider = 4; 
    uint16_t extra_delay = 0;

    //cycle 0 is for synchronous reset
    uint16_t cs_on        = 0;
    uint16_t aad_oe_on    = cs_on;
    uint16_t aad_oe_off   = aad_oe_on + 1;
    
    //adv is just one low pulse
    uint16_t aad_adv_on   = 0;
    uint16_t aad_adv_off  = aad_oe_off;
    uint16_t adv_on       = aad_adv_off;
    uint16_t adv_off      = adv_on + 1; 
 
    //write begin
    uint16_t we_assert    = adv_off;
    uint16_t data_bus    = we_assert; 
    uint16_t access_time  = 1; //cycles to access each data
    uint16_t write_access = data_bus +  access_time + 1;  //when slave reads the data
    //write end
    uint16_t write_csoff  = write_access + 1; //Rule 7
    uint16_t we_deassert  = write_csoff; 
    uint16_t write_cycles = write_csoff; 

    //read begin
    uint16_t oe_assert    = adv_off;
    uint16_t read_access  = oe_assert + 2;  //When Sitara reads the data

    //read end
    uint16_t read_csoff   = read_access + 1; //Rule 7
    uint16_t oe_deassert  = read_csoff;
    uint16_t read_cycles  = read_csoff + 1; //allow OE on RFIC to switch back to address mode 

    uint16_t wait_monitor_delay = 0; // 1 extra clock wait before read

    uint16_t transaction_delay = 0;

   uint16_t granularity = 1; 
#if 0
    if (clk_divider == 4) {
      //granularity doubles RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME,
      //ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME,
      //CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE
      granularity = 2;
    }
#endif

    //configure for NOR 
    // CONFIG 1 .. 16 bits multiplexed
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG1(csNum)) = (0x0 |
        ((clk_divider -1) <<  GPMC_CONFIG1_0_GPMCFCLKDIVIDER_SHIFT) |
        ((granularity -1) <<  GPMC_CONFIG1_0_TIMEPARAGRANULARITY_SHIFT) |
        (0x1 << GPMC_CONFIG1_0_MUXADDDATA_SHIFT ) |
        (GPMC_CONFIG1_0_DEVICESIZE_SIXTEENBITS <<  GPMC_CONFIG1_0_DEVICESIZE_SHIFT ) |
        (0 << GPMC_CONFIG1_0_CLKACTIVATIONTIME_SHIFT) |
        (wait_monitor_delay << GPMC_CONFIG1_0_WAITMONITORINGTIME_SHIFT) |
        (0x1 << GPMC_CONFIG1_0_WAITWRITEMONITORING_SHIFT) |
        (0x1 << GPMC_CONFIG1_0_WAITREADMONITORING_SHIFT) |
        (0x0 << GPMC_CONFIG1_0_DEVICETYPE_SHIFT) |
        (2 << GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_SHIFT ) |
        (1 << GPMC_CONFIG1_0_WRITETYPE_SHIFT) |
        (1 << GPMC_CONFIG1_0_READTYPE_SHIFT) |
        (burst_en << GPMC_CONFIG1_0_READMULTIPLE_SHIFT) |
        (burst_en << GPMC_CONFIG1_0_WRITEMULTIPLE_SHIFT) |
        0);	



   
    uint16_t  mult = (clk_divider / (granularity));

    // config 2 .. chip select assert/deassert times
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG2(csNum)) = (0x0 |
        ((cs_on * mult) << GPMC_CONFIG2_0_CSONTIME_SHIFT) |	// CS_ON_TIME 
        (extra_delay << GPMC_CONFIG2_0_CSEXTRADELAY_SHIFT) |
        ((read_csoff * mult) << GPMC_CONFIG2_0_CSRDOFFTIME_SHIFT) |	// CS_DEASSERT_RD
        ((write_csoff * mult) << GPMC_CONFIG2_0_CSWROFFTIME_SHIFT));	//CS_DEASSERT_WR

    // config 3 .. latch enable assert and de-assert
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG3(csNum)) = (0x0 |
        ((adv_on * mult) << GPMC_CONFIG3_0_ADVONTIME_SHIFT) | //ADV_ASSERT
        (extra_delay << GPMC_CONFIG3_0_ADVEXTRADELAY_SHIFT) |
        ((adv_off * mult) << GPMC_CONFIG3_0_ADVRDOFFTIME_SHIFT) | //ADV_DEASSERT_RD
        ((adv_off * mult) << GPMC_CONFIG3_0_ADVWROFFTIME_SHIFT) | //ADV_DEASSERT_WR
        ((aad_adv_on * mult) << GPMC_CONFIG3_0_ADVAADMUXONTIME_SHIFT) |
        ((aad_adv_off * mult) << GPMC_CONFIG3_0_ADVAADMUXRDOFFTIME_SHIFT) |
        ((aad_adv_off * mult) << GPMC_CONFIG3_0_ADVAADMUXWROFFTIME_SHIFT) |
	0); 

    // config 4 .. output enable / read write enable assert and de-assert
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG4(csNum)) = (0x0 |
        (extra_delay << GPMC_CONFIG4_0_OEEXTRADELAY_SHIFT) |
        (extra_delay << GPMC_CONFIG4_0_WEEXTRADELAY_SHIFT) |
        ((oe_assert * mult) << GPMC_CONFIG4_0_OEONTIME_SHIFT) |	//OE_ASSERT
        ((oe_deassert * mult) << GPMC_CONFIG4_0_OEOFFTIME_SHIFT) |	//OE_DEASSERT
        ((we_assert * mult) << GPMC_CONFIG4_0_WEONTIME_SHIFT)| //WE_ASSERT
        ((we_deassert * mult) << GPMC_CONFIG4_0_WEOFFTIME_SHIFT) | //WE_DEASSERT
	((aad_oe_off * mult) << GPMC_CONFIG4_0_OEAADMUXOFFTIME_SHIFT) |
	((aad_oe_on * mult) << GPMC_CONFIG4_0_OEAADMUXONTIME_SHIFT)
	); 
    // Config 5 - read and write cycle time
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG5(csNum)) = (0x0 |
        ((read_cycles * mult) << GPMC_CONFIG5_0_RDCYCLETIME_SHIFT)|	//CFG_5_RD_CYCLE_TIM XXX
        ((write_cycles * mult) << GPMC_CONFIG5_0_WRCYCLETIME_SHIFT)|	//CFG_5_WR_CYCLE_TIM 
        ((read_access * mult) << GPMC_CONFIG5_0_RDACCESSTIME_SHIFT)|          // CFG_5_RD_ACCESS_TIM XXX
        ((access_time * mult)  << GPMC_CONFIG5_0_PAGEBURSTACCESSTIME_SHIFT));  

    //force write data on rising edge 
    int fix = 1;
    if (clk_divider == 1) {
      fix = 0;
    }


    // Config 6 .. bus turnaround delay, etc
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG6(csNum)) = (0x0 |
        (((transaction_delay) ? 1 : 0) << GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_SHIFT) |
        ((transaction_delay * mult) << GPMC_CONFIG6_0_CYCLE2CYCLEDELAY_SHIFT) |
        ((data_bus * mult) << GPMC_CONFIG6_0_WRDATAONADMUXBUS_SHIFT)| //WR_DATA_ON_ADMUX 
        ((write_access * mult - fix ) << GPMC_CONFIG6_0_WRACCESSTIME_SHIFT));  //CFG_6_WR_ACCESS_TIM

    // config 7 .. base address of the chip select and address space.
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(csNum)) =
        ( base << 4 << GPMC_CONFIG7_0_BASEADDRESS_SHIFT) | //base address mask
        (0x1 << GPMC_CONFIG7_0_CSVALID_SHIFT) | //enable
        (0x0 << GPMC_CONFIG7_0_MASKADDRESS_SHIFT);  //256Mb


}

void gpmc_init()
{


    //enable clock to GPMC module
    HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL ) |=
                CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE;
    //check to see if enabled
    while((HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL) & CM_PER_GPMC_CLKCTRL_IDLEST) !=
                (CM_PER_GPMC_CLKCTRL_IDLEST_FUNC << CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT));


    //reset the GPMC module
    HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG ) |= GPMC_SYSCONFIG_SOFTRESET;
    while((HWREG(SOC_GPMC_0_REGS + GPMC_SYSSTATUS) & GPMC_SYSSTATUS_RESETDONE) ==
                GPMC_SYSSTATUS_RESETDONE_RSTONGOING);


    //disable all CSn
    for (int i = 0; i < 8; i++) {
      HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(i)) = 0;
    }

    HWREG(SOC_GPMC_0_REGS + GPMC_SYSCONFIG) = 0x11;
    HWREG(SOC_GPMC_0_REGS + GPMC_IRQENABLE) = 0x0;
    HWREG(SOC_GPMC_0_REGS + GPMC_TIMEOUT_CONTROL) = GPMC_TIMEOUT_CONTROL_TIMEOUTSTARTVALUE;
#ifndef CSC_FPGA
    HWREG(SOC_GPMC_0_REGS + GPMC_TIMEOUT_CONTROL) = GPMC_TIMEOUT_CONTROL_TIMEOUTSTARTVALUE | 1; //enable timeout
#endif

    gpmc_init_cs(1, 0, 1); //single @ 0x10000000 (256Mb)
    gpmc_init_cs(2, 1, 0); //burst @ 0x0 
    //The first 1MB of address space 0x0-0xFFFFF is inaccessible externally.
}

uint16_t mymem[0x10000];

void gpmc_dump(int cs)
{

  printf("GPMC_SYSCONFIG=0x%08x\n",GPMCREG(GPMC_SYSCONFIG));
  printf("GPMC_TIMEOUT_CONTROL=0x%08x\n",GPMCREG(GPMC_TIMEOUT_CONTROL));
  printf("GPMC_IRQENABLE=0x%08x\n",GPMCREG(GPMC_IRQENABLE));
  printf("GPMC_CONFIG=0x%08x\n",GPMCREG(GPMC_CONFIG));

  printf("CSn=%d....\n", cs);
  printf("GPMC_CONFIG1_CSn=0x%08x\n", GPMCREG(GPMC_CONFIG1(cs)));
  printf("GPMC_CONFIG2_CSn=0x%08x\n", GPMCREG(GPMC_CONFIG2(cs)));
  printf("GPMC_CONFIG3_CSn=0x%08x\n", GPMCREG(GPMC_CONFIG3(cs)));
  printf("GPMC_CONFIG4_CSn=0x%08x\n", GPMCREG(GPMC_CONFIG4(cs)));
  printf("GPMC_CONFIG5_CSn=0x%08x\n", GPMCREG(GPMC_CONFIG5(cs)));
  printf("GPMC_CONFIG6_CSn=0x%08x\n", GPMCREG(GPMC_CONFIG6(cs)));
  printf("GPMC_CONFIG7_CSn=0x%08x\n", GPMCREG(GPMC_CONFIG7(cs)));
}

int main(int argc, char** argv)
{
    int fd = open("/dev/mem", O_RDWR|O_SYNC); //O_SYNC makes the memory uncacheable
#if 1
    __mmapl = (uint32_t*) mmap(NULL, 0x20000000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, MMAP_OFFSET);

    //gpmc_dump(6);
    gpmc_init();
    gpmc_dump(2);
#endif


#if 1
    volatile uint8_t *extmem;
    extmem = (uint8_t *) mmap(NULL,0x10000000, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x10000000);
    volatile uint32_t * p32 = (uint32_t *) &extmem[0x100020];
    *p32 = 0xdeadbeef;
    uint32_t val = *p32;
    *p32 = 0xcafebabe;
    uint32_t val2 = *p32;
		printf("val=%#x\n", val);
		printf("val=%#x\n", val2);
 
    //printf("size=%d\n", sizeof(buffer));
    //memcpy(extmem, buffer, sizeof(buffer)-1);

#endif
    return(0) ;
}