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AM5728 　MPU C0/C1 Enable/Disable

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM5728

Hi,

I have one question regarding AM5728 processor.

As you know, AM572x has two MPU cores. My customer would like to change MPU0/1 enable setting directly by using PM_CPU1_PWRSTCTRL[1:0] and [7]  bit.

Customer tried to changethe PM_CPU1_PWRSTCTRL register directly by using Jtag emulator. But  the value of PM_CPU1_PWRSTST register

sometimes changed, and sometimes not changed. Why?

AM572x TRM Table 4-5 MPU_Cx State Transitons shows  software requirement for changing MPU core. But customer needs more detailed information. Are there any sample source code for this?

I appreciate your quick reply.


Best regards,

Michi

  • 0
    TI__Guru**** 393215 points
    I will ask the AM57X team to comment.
  • 0
    TI__Mastermind 29520 points
    Hello Michi,

    The MPU subsystem provides a high-performance computing platform with high peak-computing performance and low memory latency, while also supporting a configuration to shut off one core and run the other at low voltage and low frequency to achieve low-power operation.
    Low power features are only applicable for MPU1 core.

    Set the PM_CPU1_PWRSTCTRL[1:0] POWERSTATE bit field to 0x0 (OFF state).
    Set the PM_CPU1_PWRSTCTRL[7] FORCED_OFF bit to 0x1.

    FORCED_OFF mode applies only to MPU_C1. In this mode, it is critically important for software to clear the SMP bit of the targeted MPU core to take that MPU core out of coherency and to prevent TLB, BTB, or instruction cache maintenance operations from other MPU core in the cluster being issued to this MPU core. The SMP bit is part of the Auxiliary Control Register (ACTLR); there is one ACTLR per MPU core. The ACTLR is a CP15 register. For more information about this register, see the ARM Cortex-A15
    Technical Reference Manual (available at infocenter.arm.com/help/index.jsp).

    Best regards,
    Yanko
  • 0 in reply to Yanko Todorov-XID
    Guru 10030 points
    Dear Yanko-san,

    Thank you for your support.

    I would like to confirm your advice.

    > Set the PM_CPU1_PWRSTCTRL[1:0] POWERSTATE bit field to 0x0 (OFF state).
    > Set the PM_CPU1_PWRSTCTRL[7] FORCED_OFF bit to 0x1.

    The above register's setting is needed for MPU1 core disable.
    And SMP bit of ACTLR register must be cleared before the above register setting.
    ACTLR register can access via CP15 regiser.

    Is my understanding right?
    Do you have sample source code for changing core setting?

    I appreciate your quick reply.

    Best regards,
    Michi
  • 0 in reply to Michi Yama
    TI__Guru**** 161600 points
    Hi Michi,

    Besides what Yanko said, & what is described in TRM (prcm chapter), you can use the Linux kernel documentation: Documentation/cpu-hotplug.txt

    Also you can test this with the linux sysfs, i.e. try:

    cd /sys/devices/system/cpu/cpu1
    root@am57xx-evm:/sys/devices/system/cpu/cpu1# echo 0 > online /* This should shutdown CPU1 it won't be visible in */
    /* /proc/cpuinfo */
    Track down the kernel code which handles the above user space command and you will see what is the sequence used for shutting down CPUs in Linux.

    I am not aware of a bare-metal sample code about this.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 10030 points
    Hi, Yordan-san,

    Thank you for your support.

    Is there someone to confirm "FORCED_OFF" bit is effective or not?
    I don't have AM5728 EVM. So I can't test it.

    If someoe can test it, please send me its test result and code.

    I appreciate your quick reply.

    Best regards,
    Michi
  • 0 in reply to Michi Yama
    TI__Guru**** 161600 points
    Hi Michi,

    I tested this on AM572x EVM. The register is available fro read/write.

    When I try to write 0x00030184 in PM_CPU1_PWRSTCTRL, which sets:

    PM_CPU1_PWRSTCTRL[1:0] POWERSTATE bit field to 0x0 (OFF state)
    PM_CPU1_PWRSTCTRL[7] FORCED_OFF bit to 0x1

    the board becomes unresponsive, no console activity, no response from touchscreen (matrix gui). I need to reset it in order to come back from this state:

    root@am57xx-evm:~# devmem2 0x48243800
    /dev/mem opened.
    Memory mapped at address 0xb6fb2000.
    Read at address 0x48243800 (0xb6fb2800): 0x00030107
    root@am57xx-evm:~# devmem2 0x48243800 w 0x00030184
    /dev/mem opened. //board hangs here

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 10030 points

    Dear Yordan-san,

    Thank you for your test and reply.

    > PM_CPU1_PWRSTCTRL[1:0] POWERSTATE bit field to 0x0 (OFF state) 
    > PM_CPU1_PWRSTCTRL[7] FORCED_OFF bit to 0x1

    You set the both POWERSTATE bit and FORCED_OFF bit. I think this is "WFI/FORCED_OFF" mode.

    How about "WFI/OFF"? What is the difference WFI/FORCED_OFF and WFI/OFF mode?

    WFI/FORCED_OFF mode : MPU_C1 core is stopped and Power off

    WFI/OFF mode  : MPU_C1 core is stopped (MPU clock is disabled) and still Power on

    Is my understanding right?

    Please advise me.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Guru**** 161600 points

    Hi Michi,

    The difference between the two low power modes is explained in AM57xx TRM.

    WFI/FORCED_OFF mode:

    "FORCED_OFF mode applies only to MPU_C1. In this mode, it is critically important for software to clear the SMP bit of the targeted MPU core to take that MPU core out of coherency and to prevent TLB, BTB, or instruction cache maintenance operations from other MPU core in the cluster being issued to this MPU core. The SMP bit is part of the Auxiliary Control Register (ACTLR); there is one ACTLR per MPU core. The ACTLR is a CP15 register. For more information about this register, see the ARM Cortex-A15 Technical Reference Manual (available at infocenter.arm.com/help/index.jsp)."

    WFI/OFF mode: 
    "In OFF and RETENTION low-power states, the standby controller gates the clock to the MPU_CLUSTERby deasserting the CLKEN signal before signaling the MPU_PRCM to perform a power transition. In theselow-power states, the MPU core can be wakened only by the MPU_PRCM. A number of important actions must be performed by software before entering such a state" 

    See Section 4.3.7.2 Power States of MPU_Cx for more details. 

    Best Regards, 
    Yordan