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AM572x EVM support for Ethernet on C66 DSP Core almost working...

Kevin Halloran
Expert 1345 points
Other Parts Discussed in Thread: SYSBIOS

I recently got the NIMU_BasicExample_evmAM572x_armExampleproject example working on the M4.  I really need it on the DSP which is not supported at the moment by the PDK.  In looking at the PDK code it looks like everything is there for it, just the build files needed to be modified in the transport nimu section.

I modified them and successfully built a c66 library, rebuilt the NDK in debug mode and modified the NIMU_BasicExample_evmAM572x_armExampleproject for the c66 DSP.  It is almost working, just need a little guidance with regards to interrupts.  Upon execution tasking is working fine as is the setup of the Ethernet PHY but when attempting to map the interrupts I am getting an E_invalidIntNum: Invalid interrupt number.  I am using:

CSL_xbarDspIrqConfigure(1,CSL_XBAR_INST_DSP1_IRQ_75, CSL_XBAR_GMAC_SW_IRQ_RX_PULSE);
CSL_xbarDspIrqConfigure(1,CSL_XBAR_INST_DSP1_IRQ_76, CSL_XBAR_GMAC_SW_IRQ_TX_PULSE);

#define GMAC_SW_IRQ_RX_PULSE_INT_NUM (75) 
#define GMAC_SW_IRQ_TX_PULSE_INT_NUM (76)
#define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (77)
#define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (78)

CPSW_Config CPSW_config =
{
CSL_DSP_ISS_REGS,
CSL_DSP_IMDIO_REGS,
CSL_DSP_IWR_REGS,
CSL_DSP_IALE_REGS,
CSL_DSP_ICPDMA_REGS,
(CSL_DSP_ISS_REGS + 0x2000U),
CSL_DSP_IPORT_REGS,
(CSL_DSP_ISS_REGS + 0x900U),
GMAC_SW_IRQ_RX_PULSE_INT_NUM,
GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM,
GMAC_SW_IRQ_TX_PULSE_INT_NUM,
GMAC_SW_IRQ_MISC_PULSE_INT_NUM,
{
{
CSL_DSP_IPORT_REGS,
CSL_DSP_ISL1_REGS,
0U,

},
{
CSL_DSP_IPORT_REGS,
CSL_DSP_ISL2_REGS,
1U,

}
}
};

Test program output:

[C66xx_DSP1] enter main()
Invoke Task_create().
Task_create().
Main task created.
start bios...


SYS/BIOS Ethernet/IP (CPSW) Sample application

Using MAC Address: ea-da-74-aa-6f-47
SetPhyMode:000021E1 Auto:1, FD10:64, HD10:32, FD100:256, HD100:128, FD1000:8192 LPBK:0
SetPhyMode:000021E1 Auto:1, FD10:64, HD10:32, FD100:256, HD100:128, FD1000:8192 LPBK:0
ti.sysbios.family.c64p.Hwi: line 189: E_invalidIntNum: Invalid interrupt number: intr# 75
Error setting up Rx Interrupts
ti.sysbios.family.c64p.Hwi: line 189: E_invalidIntNum: Invalid interrupt number: intr# 76
Error setting up Rx Interrupts
EMAC has been started successfully
Registeration of the EMAC Successful
Network Added: If-1:192.168.1.4
exit taskFxn()
ENETPHY_FindingState: PhyNum: 1
ENETPHY_FindingState: PhyNum: 2
ENETPHY_DisablePhy(1)
Enable Phy to negotiate external connection
NWAY Advertising: FullDuplex-1000 FullDuplex-100 HalfDuplex-100 FullDuplex-10 HalfDuplex-10
ENETPHY_DisablePhy(2)
Enable Phy to negotiate external connection
NWAY Advertising: FullDuplex-1000 FullDuplex-100 HalfDuplex-100 FullDuplex-10 HalfDuplex-10
Negotiated connection: FullDuplex 1000 Mbs

  • 0
    TI__Guru**** 393215 points
    I will ask the RTOS team to look at this.
  • 0 in reply to Biser Gatchev-XID
    Expert 1345 points
    Some added info. It is failing within cpsw_ethdriver.c, Interrupt_init. I stepped through the code and looks like Sys/Bios can't map the interrupt which referencing the manual looks correct? Failure appears to not be in the NIMU code but low level interrupt mapping of Hwi_construct(). Possibly I'm interpreting the available interrupt number improperly?

    Also I believe there is a bug in

    HwiP_tirtos.c:
    HwiP_Handle HwiP_create(int32_t interruptNum, HwiP_Fxn hwiFxn,
    HwiP_Params *params)

    and Interrupt_init(). You always get the message

    Error setting up Rx Interrupts
    Error setting up Rx Interrupts -> this should be Tx as well.

    Because the function HwiP_create (NIMU_osalRegisterInterrupt) always returns a pointer to a malloced block, regardless of whether it is successful or not. It should return NULL on failure and free the malloced block when Hwi_construct fails as this could be a small memory leak if code continually tried to initialize. Leak might get handled further downstream but the status message is wrong as it always appears, on good and bad interrupt mappings.

    In cpsw_ethdriver.c:

    /**
    * @b Interrupt_init
    * @n
    * Registering Interrupts and Enabling global interrupts.
    *
    * @param[in] void
    *
    * @retval
    * void
    */
    void Interrupt_init(void)
    {
    HwiP_Handle rxHwiHandle;
    HwiP_Handle txHwiHandle;
    static Uint32 cookie = 0;

    cookie = NIMU_osalHardwareIntDisable();

    HwiP_Params hwiParams;

    NIMU_osalHwiParamsInit(&hwiParams);

    hwiParams.arg = (uintptr_t)NULL;
    hwiParams.evtId = CPSW_config.rxIntrNum;
    hwiParams.priority = 0x20; //TODO Rename
    rxHwiHandle = NIMU_osalRegisterInterrupt(CPSW_config.rxIntrNum, &Cpsw_HwIntRx, &hwiParams);
    if(rxHwiHandle != NULL)
    NIMU_drv_log("Error setting up Rx Interrupts \n");

    hwiParams.arg = (uintptr_t)NULL;
    hwiParams.evtId = CPSW_config.txIntrNum;
    hwiParams.priority = 0x20; //TODO Rename
    txHwiHandle = NIMU_osalRegisterInterrupt(CPSW_config.txIntrNum, &Cpsw_HwIntTx, &hwiParams);
    if(txHwiHandle != NULL)
    NIMU_drv_log("Error setting up Rx Interrupts \n");

    /* Restore global interrupts */
    NIMU_osalHardwareIntRestore(cookie);
    }
  • 0 in reply to Biser Gatchev-XID
    Expert 1345 points
    Bit more testing. If set as below the interrupts map properly in Hwi_create, without error, but I'm sure I have the XBAR mapping messed up as I do not DMA any RX interrupts. Looking at the sysbios source hwi will allow 4 to 15 as an interrupt number for mapping.

    CSL_xbarDspIrqConfigure(1,CSL_XBAR_INST_DSP1_IRQ_35, CSL_XBAR_GMAC_SW_IRQ_RX_PULSE);
    CSL_xbarDspIrqConfigure(1,CSL_XBAR_INST_DSP1_IRQ_36, CSL_XBAR_GMAC_SW_IRQ_TX_PULSE);



    #define GMAC_SW_IRQ_RX_PULSE_INT_NUM (4)
    #define GMAC_SW_IRQ_TX_PULSE_INT_NUM (5)
    #define GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM (6)
    #define GMAC_SW_IRQ_MISC_PULSE_INT_NUM (7)

    CPSW_Config CPSW_config =
    {
    CSL_DSP_ISS_REGS,
    CSL_DSP_IMDIO_REGS,
    CSL_DSP_IWR_REGS,
    CSL_DSP_IALE_REGS,
    CSL_DSP_ICPDMA_REGS,
    (CSL_DSP_ISS_REGS + 0x2000U),
    CSL_DSP_IPORT_REGS,
    (CSL_DSP_ISS_REGS + 0x900U),
    GMAC_SW_IRQ_RX_PULSE_INT_NUM,
    GMAC_SW_IRQ_RX_THRESH_PULSE_INT_NUM,
    GMAC_SW_IRQ_TX_PULSE_INT_NUM,
    GMAC_SW_IRQ_MISC_PULSE_INT_NUM,
    {
    {
    CSL_DSP_IPORT_REGS,
    CSL_DSP_ISL1_REGS,
    0U,

    },
    {
    CSL_DSP_IPORT_REGS,
    CSL_DSP_ISL2_REGS,
    1U,

    }
    }
    };