Hello,
This topic concerns DDR settings changes after the first suspend / resume cycle. Could be interesting to anyone experiencing memory issues after suspend / resume.
I made a custom design based on am335x-evmsk using the same ddr3 form micron. The differences between both design are that the routing and board stackup are different, from the DDR standpoint.
I have noticed unstabilities, more specifically memory-related kernel crashes after the first suspend / resume cycle (either in "mem" or "standby").
After days of investigation I discovered that the DDR io ctrl / pads settings are changed by the suspend / resume cycle (Using the latest CM3 firmware version) :
Before suspend those registers are (values programmed by the uboot bootloader in sdram_init of board/ti/am335x/board.c):
ddr_cmd0_ioctrl : 0x0000018b
ddr_cmd1_ioctrl : 0x0000018b
ddr_cmd2_ioctrl : 0x0000018b
ddr_data0_ioctrl : 0x0000018b
ddr_data1_ioctrl : 0x0000018b
After resume those registers are:
ddr_cmd0_ioctrl : 0x0000018b
ddr_cmd1_ioctrl : 0x00000000
ddr_cmd2_ioctrl : 0x00000000
ddr_data0_ioctrl : 0x00000084
ddr_data1_ioctrl : 0x00000084
I realized those changes were done by the CM3 firmware, see below an extract of the resume routine for ddr of the CM3 source code (pm_services/ddr.c, function ddr_io_resume)
if (mem_type == MEM_TYPE_DDR3) {
/* Disable the pull for CMD2/1/0 */
__raw_writel(RESUME_IO_PULL_CMD_DDR3, DDR_CMD2_IOCTRL);
__raw_writel(RESUME_IO_PULL_CMD_DDR3, DDR_CMD1_IOCTRL);
/* Disable the pull for DATA1/0 */
__raw_writel(RESUME_IO_PULL_DATA_DDR3, DDR_DATA0_IOCTRL);
__raw_writel(RESUME_IO_PULL_DATA_DDR3, DDR_DATA1_IOCTRL);
if (soc_id == AM43XX_SOC_ID) {
__raw_writel(RESUME_IO_PULL_DATA_DDR3, DDR_DATA2_IOCTRL);
__raw_writel(RESUME_IO_PULL_DATA_DDR3, DDR_DATA3_IOCTRL);
}
Changing this code to have the same values (ie 0x18b) programmed by the bootloader solved all my issues.
Those changes are also observed on the EVMSK but do not lead to any type of memory corruption issue. But on my custom design they do.
1) Is this the best place to fine-tune hw settings for the DDR, and should not those be programmed in the bootloader ?
To me, the suspend/resume cycle functions in the CM3 firmware should not be used to "tune" hw settings for normal operation, but only to :
- program hw settings while the platform is in low power,
- revert back to pre-suspend configuration.
Please let me know your thoughts. Anyone seeking to fine tune their hw settings for their design will take some time before discovering they are reprogrammed by the CM3 firmware.
2) I am not even sure those settings changes are relevant since they disagree with the rule
"Values for DDR_CMDx_IOCTRL.io_config_sr_clk should be programmed to the same value"
in section 9.2.5 DDR PHY of the TRM.
In the code excerpt above, the changes concern only CMD2 and CMD1 but not CMD0 leading to inconsistencies betweem them after the resume cycle :
ddr_cmd0_ioctrl : 0x0000018b
ddr_cmd1_ioctrl : 0x00000000
ddr_cmd2_ioctrl : 0x00000000
Please advise,
Best Regards,
Gregoire
