AM335x early boot problem (SPL/ MLO)

Biser,

now I have conducted this suggested DDR-RAM tuning process. As I use the same MT41K256M16HA-125:E memories like the BBB I get the same configuration register values as in the example. For DQS and CK trace lengths of 0.865 and 0.914 inches also the same results as in the example are calculted except _WR_DQS_SLAVE_RATIO was calculated to 0.

The resulting .gel-file snippet is:

//******************************************************************
//DDR3=400MHz
//OPP100
//******************************************************************

//******************************************************************* 
//DDR3 PHY parameters
//*******************************************************************
// DDR3 400MHz settings 
#define  CMD_PHY_CTRL_SLAVE_RATIO       0x80
#define  CMD_PHY_INVERT_CLKOUT          0x0

#define  DATA_PHY_RD_DQS_SLAVE_RATIO    0x40
#define  DATA_PHY_FIFO_WE_SLAVE_RATIO   0x70 //RD DQS GATE
#define  DATA_PHY_WR_DQS_SLAVE_RATIO    0x0
#define  DATA_PHY_WR_DATA_SLAVE_RATIO   0x80  //WRITE DATA

#define  DDR_IOCTRL_VALUE               (0x18B)

//******************************************************************
//EMIF parameters
//******************************************************************
// DDR3 400MHz settings -- Needs modified

#define ALLOPP_DDR3_READ_LATENCY    0x07        //RD_Latency = (CL + 2) - 1

//400MHz settings for 4Gb device -- Needs modified
#define ALLOPP_DDR3_SDRAM_TIMING1   0x0AAAD4DB
#define ALLOPP_DDR3_SDRAM_TIMING2   0x266B7FDA   
#define ALLOPP_DDR3_SDRAM_TIMING3   0x501F867F

#define ALLOPP_DDR3_SDRAM_CONFIG    0x61C05332  //termination = 1 (RZQ/4)
                                                //dynamic ODT = 2 (RZQ/2)
                                                //SDRAM drive = 0 (RZQ/6)
                                                //CWL = 0 (CAS write latency = 5)
                                                //CL = 4 (CAS latency = 6)
                                                //ROWSIZE = 6 (15 row bits)
                                                //PAGESIZE = 2 (10 column bits)
#define ALLOPP_DDR3_REF_CTRL        0x00000C30  //400 * 7.8us = 0xC30
#define ALLOPP_DDR3_ZQ_CONFIG       0x50074BE4

The electronics is built after figure 7-48 in the AM335x datasheet with 240R ZQ-resistor.

As the DDR3_slave_ratio_search_auto.out-program runs, only zeroes are produced. What should I check or change to bring the memory to function?

Thanks and regards

Arndt

Biser,

thanks. eventually I didn't do that part thoroughly enough. At least the tracks are designed to 50 Ohms and the lengths are as follows (all in millimeters):

Regards

Arndt

Ok. It's not 500mils skew because Reset and Termination should not be integrity critical signals. But nevertheless the specification is not met as we have 145 mils skew in address lines (e.g.).
But why this problem occurs in this early initialization state before SDRAM-settings are applied to the board? The evm-example in u-boot first detects the board type and then applies DDR2 or DDR3-settings of different kind. Is this generally possible or should it be avoided?
Best Regards
Arndt

Hello Arndt,

Could you attach one log from the terminal with the defined debug flag in <u-boot>/include/configs/ti_armv7_common.h

#define DEBUG

Best regards,
Kemal

Biser, sorry it's vice versa and bits 2,3,4 and 14 are not pulled to ground but all others.

Kind regards

Arndt

Biser,

here it is. "nicht bestücken" means "do not install".

Regards

Arndt

Edit: Customer schematic removed.

Ok, we have additionally provided those 2 resistors but no visible change in board behaviour - still no reaction from MLO.

Regards

Arndt

Biser thanks,

after releasing the RTC reset line the system boots up MLO, u-boot and finally linux. Cool.

Many thanks and regards

Arndt