AM335x GPIO input slow rise/fall times

Hi, Biser,

Schmidt triggers can help prevenet unexpected output toggle if there is glitch during input sigal rising or falling stage. But as said in many material, if the input signals level crosses the logic threshold at a very slow edge, both PMOS and NMOS in the chip input stage might be ON simulataneous for a long time. The current is big when both PMOS and NMOS are ON, long-time big current may bring damage to the chip. Can AM335X schmidt input protect the chip from this slow input edge impact?

Thanks,

Peng,

Yes, actually you are correct. We noticed that my previous reply was not accurate. This is being checked internally and additional information will be posted here when available.

Hi, Paul,

What kind of buffer do you recommend to use? a Schmitt buffer like NL17SG?

www.onsemi.com/.../NL17SG17-D.PDF

Interesting is that I see in the data sheet of NL17SG, there is no limit to rise/fall time, so wondering why AM335X Schmitt input is not the same case.

Regards,

Peng,

Hi Paul-san,

I have the same question.

What is the maximum input transition rise or fail rate to prevent latch-up condition?

Best regards,

Daisuke

Hi Paul-san,

I check the TI application report for standard logic. The maximum input transition rise or fail rate for the LV devices with hysteresis characteristics is 100 ns/V.

http://www.ti.com/lit/an/scba004c/scba004c.pdf

For AM335x, Is the transition rate in 100 ns/V allowed?

Best regards,

Daisuke

Hi, Paul-san,

Is the hysteresis also implemented on the McSPI interface?

In the AM335X datasheet, the McSPI input signal transition time is 5ns, this is too short. Is that 100ns/V also applicable to McSPI input?

Peng,

Daisuke,

I do not have enough data to answer your original question at this time.  However, you should not assume the TI application report for standard logic applies to AM335x. It is very unlikely TI standard logic devices are built using the same semiconductor process node as AM335x.

You should always comply to the maximum rise/fall times specified for any peripheral interfaces which define these parameters. When defined, the maximum rise/fall times provided in the data sheet were the limits used by the design team to close timing for all other timing parameters of the respective peripheral.

You should minimize the rise/fall times as much as possible for peripherals that do not define the maximum rise/fall times.

Peng,

The hysteresis of each input is defined in the DC Electrical Characteristics table of the data sheet.

As I explained above, the maximum rise/fall times provided in the data sheet were the limits used by the design team to close timing for all other timing parameters of the respective peripheral.  The peripheral interface may not work as expected under all operating conditions defined in the data sheet if you do not comply with the maximum rise/fall time requirement.

I also addressed your question about 100ns/V above.  The TI application report  for standard logic where Daisuke found this reference does not apply to AM335x.

Regards,
Paul

Hi, Paul-san,

Thank you for your reply.

The maximum transition time defined for GMII[x]_RXCLK and GMII[x]_TXCLK inputs is 5ns.

For all peripheral inputs which do not define the transition time in datasheet, is the transition time of 5ns allowed?

Best regards,

Daisuke

Hi, Paul-san,

Thank you for your reply.

Best regards,

Daisuke