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GPIO module of AM5728

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM5728

Hi,

I would like to know the function of GPIO moudle for AM5728.

1) If MPU is in standby mode, does GPIO module stop to output signal on GPIO pin?

   Or can GPIO module keep to output the previous signal with interfance clock?

2) If MPU core is in standby mode, can GPIO module be set the register of data output?

   Or if its register can't be set, does GPIO pin keep the previous signal on GPIO pin?

Please advise me.

I appreciate your quick reply.

Best regards,

Michi

  • 0
    TI__Guru**** 393215 points
    I will ask the AM57x experts to comment. They will respond here.
  • 0
    TI__Guru**** 161600 points
    Hi Michi,

    I tested this on my AM57xx EVM.

    The gpio stops working when MPU enters standby, and it keeps the last state it was in, i.e. if gpio was high at the time MPU enters standby, then it keeps the high level (but no toggle the pin stays in 1) and vice versa if gpio was 0 (low) at the time MPU enters standby, then it keeps the 0 state.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 10030 points

    Dear Yordan-san,

    Thank you for your quick reply.

    I understood GPIO module stops working when MPU core enters standby.

    BTW, I have one more question.

    When MPU core enters standby, does EMIF controller stop working? Or can EMIF controller continue working for DDR3 memory?

    Please advise me again.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    Guru 10030 points
    Dear Yordan-san,

    Thank you for your support.

    Sorry, I have two more questions.

    1) How does MPU core standby mode reduce power consumption?

    2) When MPU core enters standby, GPIO module stops working. Does this mean that MPU can't be waked up by GPIO's interrupt?

    I appreciate your quick reply.

    Best regards,
    Michi
  • 0 in reply to Michi Yama
    TI__Guru**** 161600 points
    Hi Michi,

    When MPU core enters standby, does EMIF controller stop working? Or can EMIF controller continue working for DDR3 memory?


    The sequence is as follows:
    DDR memory is in self-refresh and contents are preserved.
    • All modules are clock gated except GPIOs
    • PLLs may be placed in bypass mode if downstream clocking does not require full performance
    • Voltage domains VDD_MPU and VDD_CORE voltage levels can be reduced to OPP50 levels because the required performance of the entire device is reduced
    • MPU power domain (PD_MPU) is in OFF state

    Emif clock is gated, but after wakup its settings are loaded again from the ddr (DDR memory is in self-refresh and contents are preserved.).

    1) How does MPU core standby mode reduce power consumption?

    See Section 8.1.4.3 Power Modes, Section 8.1.4.3.2 Standby, and the following wikis:
    processors.wiki.ti.com/.../AM335x_Power_Consumption_Summary
    processors.wiki.ti.com/.../AM335x_Power_Management_Standby_User's_Guide
    processors.wiki.ti.com/.../Sitara_Power_Management_User_Guide

    2) When MPU core enters standby, GPIO module stops working. Does this mean that MPU can't be waked up by GPIO's interrupt?

    Perhaps I wasn't clear enough, the GPIO clock is NOT gated, as stated in Section 8.1.4.3.2 Standby. What I meant to say is that just the software that toggles the GPIO is executed on the MPU, so when you suspend/standby the MPU, the code stops its execution & gpio maintains the last state it was in (high or low). So you CAN WAKE-UP the device from standby, through a GPIO.

    Best Regards,
    Yordan