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AM572x PRU Ethernet firmware

xixi
Expert 2990 points

Other Parts Discussed in Thread: AM5728, TLK105L, TPS659037

HI all:

        Just now we developed an am5728 board which refer to the am5728 IDK.

        We have modified the device-tree ，pinmux and the pru_rproc.c driver . 

        Now it can generate the eth2 and eth3 and the firmware (am57xx-pru0-prueth-fw.elf,am57xx-pru1-prueth-fw.elf) can also be loaded successfully.

        However we can not ping, and we can not see any level change on the pin PR2_MII0_TXD0~PR2_MII0_TXD3

        So we want to debug the firmware am57xx-pru0-prueth-fw.elf and I suspect the pruss2 does not work properly.

        Can you tell me how can I debug the firmware am57xx-pru0-prueth-fw.elf

Thanks

regards

        

  • 0
    TI__Guru**** 393215 points
    Hi,

    Did you bring up the ports as described in this wiki: processors.wiki.ti.com/.../PRU-ICSS_Ethernet

    "On the AM572x IDK type ifup eth2 to bring up PRU2 ETH0 and type ifup eth3 to bring up PRU2 ETH1. If all goes well you should see the PRU-ICSS ports in the output of the ifconfig command"
  • 0 in reply to Biser Gatchev-XID
    Expert 2990 points
    HI Biser

    Thanks for your reply.
    We have bring up the eth2 and eth3 and there is no use.
    Can you tell me how can I debug the firmware am57xx-pru0-prueth-fw.elf
  • 0 in reply to xixi
    TI__Guru**** 393215 points
    I have notified the PRU Ethernet team. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 43296 points
    Hi Quan,

    Can you please elaborate the modification of device-tree ，pinmux and the pru_rproc.c driver you made?

    Are you able to confirm eth2 and eth3 link up? You may need look into the drivers/net/ethernet/ti/prueth.c first before diving into PRU firmware.

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Expert 2990 points

    Hi Garrett

                    Thanks for your reply

                     My device-tree is like below

                     

    pruss2_eth {
    compatible = "ti,am57-prueth";
    pruss = <&pruss2>;
    sram = <&ocmcram1>;
    interrupt-parent = <&pruss2_intc>;

    pruss2_emac0: ethernet-mii0 {
    phy-handle = <&pruss2_eth0_phy>;
    phy-mode = "mii";
    interrupts = <20>, <22>;
    interrupt-names = "rx", "tx";
    /* Filled in by bootloader */
    local-mac-address = [00 00 00 00 00 00];
    };

    pruss2_emac1: ethernet-mii1 {
    phy-handle = <&pruss2_eth1_phy>;
    phy-mode = "mii";
    interrupts = <21>, <23>;
    interrupt-names = "rx", "tx";
    /* Filled in by bootloader */
    local-mac-address = [00 00 00 00 00 00];
    };
    };

    &mailbox3 {
    status = "okay";
    mbox_pru1_0: mbox_pru1_0 {
    status = "okay";
    };
    mbox_pru1_1: mbox_pru1_1 {
    status = "okay";
    };
    };

    &mailbox4 {
    status = "okay";
    mbox_pru2_0: mbox_pru2_0 {
    status = "okay";
    };
    mbox_pru2_1: mbox_pru2_1 {
    status = "okay";
    };
    };

    &pruss1 {
    status = "okay";
    pru1_0: pru0@4b234000 {
    mboxes = <&mailbox3 &mbox_pru1_0>;
    status = "okay";
    };

    pru1_1: pru1@4b238000 {
    mboxes = <&mailbox3 &mbox_pru1_1>;
    status = "okay";
    };
    };

    &pruss2 {
    status = "okay";
    pru2_0: pru0@4b2b4000 {
    mboxes = <&mailbox4 &mbox_pru2_0>;
    status = "okay";
    };

    pru2_1: pru1@4b2b8000 {
    mboxes = <&mailbox4 &mbox_pru2_1>;
    status = "okay";
    };
    };

    &pruss2_mdio {
    status = "okay";
    pruss2_eth0_phy: ethernet-phy@0 {
    reg = <0>;
    interrupt-parent = <&gpio2>;
    interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
    };

    pruss2_eth1_phy: ethernet-phy@1 {
    reg = <1>;
    interrupt-parent = <&gpio2>;
    interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
    };
    };

    &pruss2_mdio {
    reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>,
    <&gpio2 19 GPIO_ACTIVE_LOW>;
    reset-delay-us = <2>; /* PHY datasheet states 1uS min */
    };

  • 0 in reply to xixi
    Expert 2990 points
    Hi
    The below is my uboot's mux_data.h
    {MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
    {MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */

    {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mcasp1_axr0.pr2_mii0_rxer */
    {MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
    {MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.pr2_mii0_txen */
    {MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.pr2_mii0_txd3 */
    {MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */
    {MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.pr2_mii0_txd1 */
    {MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.pr2_mii0_txd0 */
    {MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
    {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr14.pr2_mii0_rxdv */
    {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
    {MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
    {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
    {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
    {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp2_axr3.pr2_mii0_rxlink */
    {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
    {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */

    {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
    {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
    {MCASP3_AXR0, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
    {MCASP3_AXR1, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},
    {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
    {GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
    {MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
    {MMC3_CMD, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
    {MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
    {MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
    {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
    {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
    {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
    {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
    {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
    {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
  • 0 in reply to Garrett Ding
    Expert 2990 points

    Hi
    The below is my pru_rproc.c
    /*
    * use a different firmware name for PRU cores supporting
    * PRUSS ethernet on specific boards
    */
    if (of_machine_is_compatible("ti,am3359-icev2") ||
    of_machine_is_compatible("ti,am437x-idk-evm") ||
    of_machine_is_compatible("ti,am5728-idk") ||
    of_machine_is_compatible("ti,am572x-beagle-x15") ||
    of_machine_is_compatible("ti,am5718-idk")) {
    if (use_eth_fw && (pdata->caps & PRU_FUNC_CAPS_ETHERNET))
    use_eth  = true;
    }

  • 0 in reply to xixi
    Expert 2990 points

    HI:
       

    Who can help us to analysis whether the above content is correct or not.

    because the pru ethernet is critical for us.

    Just now we can get the pru eth link info such as link is up or link is down.

    But we can not ping ip address successfully, even we can not get any voltage changing in the pin pr2 TXD0 - TXD1


    Thanks

    regards

    wang

  • 0 in reply to xixi
    TI__Mastermind 43296 points

    Wang,

    The following pins were set to PIN_OUTPUT_PULLUP in default u-boot mux_data.h, do you create your pin mux with TI pin mux tool ?

    {GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
    {MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
    {MMC3_CMD, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
    {MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
    {MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */

    After the link is up, but ping fails, you may need capture the packets with wireshark to see what's happening on the wire.


    Regards,

    Garrett

  • 0 in reply to Garrett Ding
    Expert 2990 points

    Hi Garrett

                      Thanks for you reply.

                     Just now if we use the below config code We can detect 25MHZ clock on the mii1_clk signal，and also detect high level on the mii1_txen signal occasionally

                     The test command is ping

    {GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
    {MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
    {MMC3_CMD, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
    {MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
    {MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */

                     However if we use the below config code We can detect 25MHZ clock on the mii1_clk signal，but we can not detect high level on the mii1_txen signal 

                     The test command is ping

    {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
    {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
    {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
    {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
    {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */

                    So I think the config PIN_INPUT_PULLUP is right

                     No matter what configuration we use, The pr2_mii1_txd0 ~ pr2_mii1_txd3 pin can not detect any level changing

                    It always low level.

                     We don't use the pinmux tools and just refer to the am572x_idk's code

    regards

    wang

  • 0 in reply to xixi
    Expert 2990 points

    HI all:

        Anybody guide this issue.

    Regards

    wang

  • 0 in reply to xixi
    TI__Genius 10440 points

    Which version of the Linux Processor SDK are you using?

    Please apply the attached patch (/cfs-file/__key/communityserver-discussions-components-files/791/3731.0001_2D00_debug_2D00_phy_2D00_spit_2D00_out_2D00_some_2D00_phy_2D00_registers.patch) and then provide the PHY register dump that appears in the kernel log. This is the dump from a working am572x-idk:

    [   10.437566] ==== PHY regs ===

    [   10.437693] BMCR(0x0): 0x3100

    [   10.437823] BMSR(0x1): 0x7849

    [   10.437953] PHYIDR1(0x2): 0x2000

    [   10.438083] PHYIDR2(0x3): 0xa212

    [   10.438213] CR1(0x9): 0x7800

    [   10.438343] PHYSCR(0x11): 0x108

    [   10.438473] RCSR(0x17): 0x41

    [   10.438603] LEDCR(0x18): 0x400

    [   10.438733] PHYCR(0x19): 0x8000

    [   10.438734] =================

    [   10.517581] ==== PHY regs ===

    [   10.517708] BMCR(0x0): 0x3100

    [   10.517838] BMSR(0x1): 0x7849

    [   10.517968] PHYIDR1(0x2): 0x2000

    [   10.518098] PHYIDR2(0x3): 0xa212

    [   10.518228] CR1(0x9): 0x7800

    [   10.518358] PHYSCR(0x11): 0x108

    [   10.518488] RCSR(0x17): 0x41

    [   10.518620] LEDCR(0x18): 0x400

    [   10.518748] PHYCR(0x19): 0x8001

    [   10.518749] =================

    We would like to check if you are using the correct firmware blobs. Can you post the md5sum of the two .elf files in your file system? Use the following two commands:

    md5sum /lib/firmware/ti-pruss/am57xx-pru0-prueth-fw.elf

    md5sum /lib/firmware/ti-pruss/am57xx-pru1-prueth-fw.elf

    Jason Reeder

  • 0 in reply to Jason Reeder
    Expert 2990 points

    HI Jason Reeder

        Thanks for reply.

         Please see my md5sums

         c2bde2a1470d2b0d0bdf60267b277696  /lib/firmware/ti-pruss/am57xx-pru0-prueth-fw.elf

         e8207dfbbf129f9ee3afa05c1a782931  /lib/firmware/ti-pruss/am57xx-pru1-prueth-fw.elf

         My file system is from processor sdk 3.0.

         The below is my TLK105L register 's print

    [ 9.040834] BMCR(0x0): 0x3100
    [ 9.064172] BMSR(0x1): 0x7849
    [ 9.088026] PHYIDR1(0x2): 0x2000

    [ 9.137102] PHYIDR2(0x3): 0xa212

    [ 9.175127] CR1(0x9): 0x7c00(If we reboot, sometimes the CR1 will become to 0x7800)
    [ 9.191182] PHYSCR(0x11): 0x108
    [ 9.196966] RCSR(0x17): 0x41
    [ 9.206651] LEDCR(0x18): 0x400
    [ 9.216076] PHYCR(0x19): 0x8020(If we reboot, sometimes the PHYCR will become to 0x8000)

    [ 9.340875] BMCR(0x0): 0x3100
    [ 9.351798] BMSR(0x1): 0x7849
    [ 9.363951] PHYIDR1(0x2): 0x2000
    [ 9.377407] PHYIDR2(0x3): 0xa212
    [ 9.381632] CR1(0x9): 0x7800
    [ 9.389887] PHYSCR(0x11): 0x108
    [ 9.397190] RCSR(0x17): 0x41
    [ 9.405031] LEDCR(0x18): 0x400
    [ 9.417381] PHYCR(0x19): 0x8001

     If the 100Mb ethernet connected to the eth2 or eth3, Their register RCSR(0x17)' value will become to 0x49

    Regards

    wang 

  • 0 in reply to Jason Reeder
    Expert 2990 points

    HI Jason Reeder

                                 Just Now We think the TLK105L phy have no problem because the register value is right

                                 So we want to debug the  firmware /lib/firmware/ti-pruss/am57xx-pru0-prueth-fw.elf and want to know why the am5728 txd0~txd3 pin have no signal

                                 I am not sure whether the pruss2 is working properly even though I can get the prueth's link status

                                 such as

                                 [ 33.289408] eth2: Link is Down

                                 [ 34.869496] eth2: Link is Up - 100Mbps/Full - flow control rx/tx

                                 So how can I debug the firmware /lib/firmware/ti-pruss/am57xx-pru0-prueth-fw.elf or get more debug info about the firmware

    Thanks 

    wang

  • 0 in reply to xixi
    TI__Genius 10440 points

    While I'm waiting on the response from the kernel developer, can you execute the following commands and tell me what the console output is? These are the pad control registers that configure the pin muxing for the pr2_mii0_txd[3:0] and pr2_mii1_txd[3:0] pins.

    devmem2 0x4A0036E4

    devmem2 0x4A0036E0

    devmem2 0x4A0036DC

    devmem2 0x4A0036D8

    devmem2 0x4A003788

    devmem2 0x4A003784

    devmem2 0x4A003780

    devmem2 0x4A00377C

    I have just retested on my AM572x IDK board with the Linux Processor SDK 3.0.0.4 and can confirm that both PR2_PRU0 and PR2_PRU1 Ethernet ports come up correctly and can be pinged from my host computer.

    We do not provide the source code for the PRU Ethernet firmwares.

    Jason Reeder

  • 0 in reply to Jason Reeder
    Expert 2990 points

    /dev/mem opened.
    Memory mapped at address 0xb6f83000.
    Read at address 0x4A0036E0 (0xb6f836e0): 0x0006000B
    /dev/mem opened.
    Memory mapped at address 0xb6ffb000.
    Read at address 0x4A0036E4 (0xb6ffb6e4): 0x0006000B
    /dev/mem opened.
    Memory mapped at address 0xb6f88000.
    Read at address 0x4A0036D8 (0xb6f886d8): 0x0006000B
    /dev/mem opened.
    Memory mapped at address 0xb6efe000.
    Read at address 0x4A0036DC (0xb6efe6dc): 0x0006000B
    /dev/mem opened.
    Memory mapped at address 0xb6ff9000.
    Read at address 0x4A00377C (0xb6ff977c): 0x0006000B
    /dev/mem opened.
    Memory mapped at address 0xb6ff3000.
    Read at address 0x4A003780 (0xb6ff3780): 0x0006000B
    /dev/mem opened.
    Memory mapped at address 0xb6fa5000.
    Read at address 0x4A003784 (0xb6fa5784): 0x0006000B
    /dev/mem opened.
    Memory mapped at address 0xb6fca000.
    Read at address 0x4A003788 (0xb6fca788): 0x0006000B
    /dev/mem opened.
    Memory mapped at address 0xb6fbd000.
    Read at address 0x4A00378C (0xb6fbd78c): 0x0006000B

  • 0 in reply to Jason Reeder
    Expert 2990 points

    hi jason

                   just now our custom board have two places which is different from idk board

    one is the RJ45 interface and anther is power chip.

    our power chip is tps659037 which is same to am5728evm board but not to am5728idk board.

    so whether it will have impact

    regards

    wang

  • 0 in reply to xixi
    TI__Genius 10440 points
    I have asked about the power chip and am awaiting a response.

    Would it be possible for you to move to the latest Linux Processor SDK (v3.2.0.5) and see if your problems still persist? Here is the download link: software-dl.ti.com/.../index_FDS.html

    Jason Reeder
  • 0 in reply to Jason Reeder
    Expert 2990 points

    ok,I will try it

    and now we are on holiday about 15 days

    so we will do this after 15 days

    thanks

  • 0 in reply to Jason Reeder
    Expert 2990 points
    I think the power chip could impact on the prueth
  • 0 in reply to xixi
    TI__Genius 10440 points

    The kernel developer does not think that VDD_CORE at 1.06V is an issue because it matches the nominal value in the AM572x Data Manual.

    Another thing we can check is to make sure the ICSS_CLK and ICSS_IEP_CLK are available. Both come from the DPLL_GMAC and you can check its status using this command:

    omapconf show dpll cfg


    One other question, do you know which revision of the silicon that you are using, revision 1.1 or 2.0?

    Jason Reeder

  • 0 in reply to Jason Reeder
    Expert 2990 points

    Hi Jason

                  Thanks for your reply

                  The New year holiday is finished

                   We have test the command, the attachment dpll.txt is the print info

                   Thanks

    Fullscreen dpll.txt Download 
    root@am57xx-evm:~# omapconf show dpll cfg
OMAPCONF (rev v1.72-11-g340f7dd built Fri Jul 8 20:14:19 EDT 2016)

HW Platform:
  Generic DRA74X (Flattened Device Tree)
  DRA75X ES1.1 GP Device (STANDARD performance (1.0GHz))
  TPS659038  ES2.2 

SW Build Details:
  Build:
    Version:  _____                    _____           _         _   
  Kernel:
    Version: 4.4.12-g3639bea54a
    Author: wangquan@ubuntu
    Toolchain: gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02)
    Type: #13 SMP PREEMPT
    Date: Mon Feb 6 20:43:47 PST 2017

|---------------------------------------------------------|
| DPLL Configuration         | DPLL_USB   | DPLL_PCIE_REF |
|---------------------------------------------------------|
| Status                     | Locked     | Locked        |
|                            |            |               |
| Mode                       | Lock       | Lock          |
| Automatic Control          | Auto LPST  | Auto LPST     |
|  LPST = Low-Power STop     |            |               |
|  FRST = Fast-Relock STop   |            |               |
|  LPBP = Low-Power ByPass   |            |               |
|  FRBP = Fast-Relock ByPass |            |               |
|  MNBP = MN ByPass          |            |               |
|                            |            |               |
| Sigma-Delta Divider        | 4          | 4             |
| SELFREQDCO                 | 0          | 0             |
|                            |            |               |
| Ref. Frequency (MHz)       | 20.000     | 20.000        |
| M Multiplier Factor        | 480        | 75            |
| N Divider Factor           | 9          | 0             |
| Lock Frequency (MHz)       | 960        | 1500          |
|                            |            |               |
| CLKOUT Output              |            |               |
|   Status                   | Enabled    | Gated         |
|   Clock Divider            | 2     (x2) | 15    (x2)    |
|   Clock Speed (MHz)        | 480        | 100           |
|                            |            |               |
| CLK_DCO_LDO Output         |            |               |
|   Status                   | Enabled    | N/A           |
|   Clock Speed (MHz)        | 960        |               |
|                            |            |               |
| CLKOUTX2_M2_LDO Output     |            |               |
|   Status                   | N/A        | Enabled       |
|   Clock Speed (MHz)        |            | 100           |
|                            |            |               |
|---------------------------------------------------------|

|-----------------------------------------------------------------------------------------------|
| DPLL Configuration          | DPLL_MPU   | DPLL_IVA    | DPLL_CORE  | DPLL_PER   | DPLL_ABE   |
|-----------------------------------------------------------------------------------------------|
| Status                      | Locked     | Stopped     | Locked     | Locked     | Stopped    |
|                             |            |             |            |            |            |
| Mode                        | Lock       | Lock        | Lock       | Lock       | LPBP       |
| Automatic Control           | Auto LPST  | Auto LPST   | Auto LPST  | Auto LPST  | Auto LPST  |
|  LPST = Low-Power STop      |            |             |            |            |            |
|  FRST = Fast-Relock STop    |            |             |            |            |            |
|  LPBP = Low-Power ByPass    |            |             |            |            |            |
|  FRBP = Fast-Relock ByPass  |            |             |            |            |            |
|  MNBP = MN ByPass           |            |             |            |            |            |
| Low-Power Mode              | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
|                             |            |             |            |            |            |
| Automatic Recalibration     | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Clock Ramping during Relock | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Ramping Rate (x REFCLK(s))  | 2          | 2           | 2          | 2          | 2          |
| Ramping Levels              | No Ramp    | No Ramp     | No Ramp    | No Ramp    | No Ramp    |
|                             |            |             |            |            |            |
| Bypass Clock                | CLKINPULOW | CLKINP      | CLKINP     | CLKINP     | CLKINPULOW |
| Bypass Clock Divider        | 1          | 1           |            |            |            |
| REGM4XEN Mode               | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Duty Cycle Correction (DCC) | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
|                             |            |             |            |            |            |
| Ref. Frequency (MHz)        | 20.000     | 20.000      | 20.000     | 20.000     | 20.000     |
| M Multiplier Factor         | 50         | 266         | 266        | 96         | 0          |
| N Divider Factor            | 0          | 4           | 4          | 4          | 0          |
| Lock Frequency (MHz)        | 2000       | 2128 (2128) | 2128       | 768        | 0 (0)      |
|                             |            |             |            |            |            |
| M2 Output                   |            |             |            |            |            |
|   Status                    | Enabled    | Gated       | Gated      | Gated      | Gated      |
|   Clock Divider             | 1     (x2) | 2     (x2)  | 2     (x2) | 4     (x2) | 1     (x2) |
|   Clock Speed (MHz)         | 1000       | 0 (532)     | 532        | 96         | 0 (0)      |
|                             |            |             |            |            |            |
| X2_M2 Output                |            |             |            |            |            |
|   Status                    |            |             |            | Enabled    | Gated      |
|   Clock Divider             |            |             |            | 4          | 1          |
|   Clock Speed (MHz)         |            |             |            | 192        | 0 (0)      |
|                             |            |             |            |            |            |
| X2_M3 Output                |            |             |            |            |            |
|   Status                    |            | Gated       | Gated      | Gated      | Gated      |
|   Clock Divider             |            | 1           | 1          | 1          | 1          |
|   Clock Speed (MHz)         |            | 0 (2128)    | 2128       | 768        | 0 (0)      |
|                             |            |             |            |            |            |
| H11 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      | Gated      |            |
|   Clock Divider             |            |             | 1          | 3          |            |
|   Clock Speed (MHz)         |            |             | 2128       | 256        |            |
|                             |            |             |            |            |            |
| H12 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    | Gated      |            |
|   Clock Divider             |            |             | 4          | 4          |            |
|   Clock Speed (MHz)         |            |             | 532        | 192        |            |
|                             |            |             |            |            |            |
| H13 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    | Gated      |            |
|   Clock Divider             |            |             | 62         | 4          |            |
|   Clock Speed (MHz)         |            |             | 34         | 192        |            |
|                             |            |             |            |            |            |
| H14 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    | Gated      |            |
|   Clock Divider             |            |             | 5          | 2          |            |
|   Clock Speed (MHz)         |            |             | 212        | 384        |            |
|                             |            |             |            |            |            |
| H21 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      |            |            |
|   Clock Divider             |            |             | 1          |            |            |
|   Clock Speed (MHz)         |            |             | 2128       |            |            |
|                             |            |             |            |            |            |
| H22 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      |            |            |
|   Clock Divider             |            |             | 5          |            |            |
|   Clock Speed (MHz)         |            |             | 425        |            |            |
|                             |            |             |            |            |            |
| H23 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    |            |            |
|   Clock Divider             |            |             | 4          |            |            |
|   Clock Speed (MHz)         |            |             | 532        |            |            |
|                             |            |             |            |            |            |
| H24 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      |            |            |
|   Clock Divider             |            |             | 6          |            |            |
|   Clock Speed (MHz)         |            |             | 354        |            |            |
|-----------------------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------|
| DPLL Configuration          | DPLL_EVE   | DPLL_DSP    | DPLL_GMAC  | DPLL_GPU   | DPLL_DDR   |
|-----------------------------------------------------------------------------------------------|
| Status                      | Stopped    | Stopped     | Locked     | Stopped    | Locked     |
|                             |            |             |            |            |            |
| Mode                        | LPBP       | Lock        | Lock       | LPBP       | Lock       |
| Automatic Control           | Auto LPST  | Auto LPST   | Auto LPST  | Auto LPST  | Auto LPST  |
|  LPST = Low-Power STop      |            |             |            |            |            |
|  FRST = Fast-Relock STop    |            |             |            |            |            |
|  LPBP = Low-Power ByPass    |            |             |            |            |            |
|  FRBP = Fast-Relock ByPass  |            |             |            |            |            |
|  MNBP = MN ByPass           |            |             |            |            |            |
| Low-Power Mode              | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
|                             |            |             |            |            |            |
| Automatic Recalibration     | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Clock Ramping during Relock | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Ramping Rate (x REFCLK(s))  | 2          | 2           | 2          | 2          | 2          |
| Ramping Levels              | No Ramp    | No Ramp     | No Ramp    | No Ramp    | No Ramp    |
|                             |            |             |            |            |            |
| Bypass Clock                | CLKINP     | CLKINP      | CLKINP     | CLKINP     | CLKINP     |
| Bypass Clock Divider        | 1          | 1           |            |            |            |
| REGM4XEN Mode               | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
| Duty Cycle Correction (DCC) | Disabled   | Disabled    | Disabled   | Disabled   | Disabled   |
|                             |            |             |            |            |            |
| Ref. Frequency (MHz)        | 20.000     | 20.000      | 20.000     | 20.000     | 20.000     |
| M Multiplier Factor         | 0          | 75          | 250        | 0          | 266        |
| N Divider Factor            | 0          | 1           | 4          | 0          | 4          |
| Lock Frequency (MHz)        | 0 (0)      | 1500 (1500) | 2000       | 0 (0)      | 2128       |
|                             |            |             |            |            |            |
| M2 Output                   |            |             |            |            |            |
|   Status                    | Gated      | Gated       | Enabled    | Gated      | Enabled    |
|   Clock Divider             | 1     (x2) | 1     (x2)  | 4     (x2) | 1     (x2) | 2     (x2) |
|   Clock Speed (MHz)         | 0 (0)      | 0 (750)     | 250        | 0 (0)      | 532        |
|                             |            |             |            |            |            |
| X2_M2 Output                |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
| X2_M3 Output                |            |             |            |            |            |
|   Status                    | Gated      | Gated       | Enabled    | Gated      | Gated      |
|   Clock Divider             | 1          | 3           | 10         | 1          | 1          |
|   Clock Speed (MHz)         | 0 (0)      | 0 (500)     | 200        | 0 (0)      | 2128       |
|                             |            |             |            |            |            |
| H11 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    |            | Enabled    |
|   Clock Divider             |            |             | 40         |            | 8          |
|   Clock Speed (MHz)         |            |             | 50         |            | 266        |
|                             |            |             |            |            |            |
| H12 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    |            |            |
|   Clock Divider             |            |             | 8          |            |            |
|   Clock Speed (MHz)         |            |             | 250        |            |            |
|                             |            |             |            |            |            |
| H13 Output                  |            |             |            |            |            |
|   Status                    |            |             | Enabled    |            |            |
|   Clock Divider             |            |             | 10         |            |            |
|   Clock Speed (MHz)         |            |             | 200        |            |            |
|                             |            |             |            |            |            |
| H14 Output                  |            |             |            |            |            |
|   Status                    |            |             | Gated      |            |            |
|   Clock Divider             |            |             | 1          |            |            |
|   Clock Speed (MHz)         |            |             | 2000       |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|                             |            |             |            |            |            |
|-----------------------------------------------------------------------------------------------|

omapconf: powerdm_deinit(): cpu not supported!!!
omapconf: clockdm_deinit(): cpu not supported!!!

  • 0 in reply to Jason Reeder
    Expert 2990 points

    Our am5728 revision is 1.1

  • 0 in reply to xixi
    Expert 2990 points

    root@am57xx-evm:~# omapconf show dpll cfg
    OMAPCONF (rev v1.72-11-g340f7dd built Fri Jul 8 20:14:19 EDT 2016)

    HW Platform:
      Generic DRA74X (Flattened Device Tree)
      DRA75X ES1.1 GP Device (STANDARD performance (1.0GHz))
      TPS659038  ES2.2

    SW Build Details:
      Build:
        Version:  _____                    _____           _         _  
      Kernel:
        Version: 4.4.12-g3639bea54a
        Author: wangquan@ubuntu
        Toolchain: gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02)
        Type: #13 SMP PREEMPT
        Date: Mon Feb 6 20:43:47 PST 2017

  • 0 in reply to Jason Reeder
    Expert 2990 points

    Hi jason

    Just now we read the datasheet spruhz6h.pdf and find the 30 Chapter
    There are two parts to discribe the pruss like below
    30.1 is Programmable Real-Time Unit Subsystem and Industrial Communication
    Subsystem AM572x SR2.0
    30.2 is Programmable Real-Time Unit Subsystem and Industrial Communication
    Subsystem AM572x SR1.1

    We also refer to this wiki document， it have some info about pru-icss updates.

    ICSS updates

    • CRC16/32 module
    • Increase IEP Timer compare registers from 8 to 16
    • IEP Timer updated from 32-bit timer to 64-bit timer. Register set is backward compatible.

    http://processors.wiki.ti.com/index.php/AM572x_SR1.1_to_SR2.0_Migration

    So we are confusing whether it will imapct on the prueth?

    Regards
    quan

  • 0 in reply to Jason Reeder
    Expert 2990 points

    HI all:

        Anybody guide this issue.

    Regards

    wang

  • 0 in reply to xixi
    TI__Genius 10440 points
    The PRU Ethernet firmwares that are provided for the AM5728 IDK are meant to be used on 2.0 silicon. This should have been made clear on the PRU Ethernet wiki page but it wasn't. I will make that update soon.

    The PRU-ICSS subsystems that are contained in the AM5728 1.1 silicon are more similar to the PRU-ICSS subsystem found in the AM335x device. It may be possible to use the PRU Ethernet firmwares provided in the AM335x Processor SDK to test your current board. However, the supported use case is to move to the 2.0 silicon revision of the AM5728 device.

    Jason Reeder
  • 0 in reply to Jason Reeder
    Expert 2990 points

    Hi Jason Reeder

                                 We have test the am335x's firmware

                                 It's OK

                                 Thank you for your recent support

    Regards

    wang