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AM5728: ECC with EMIF1 x8 memories

user4759774
Intellectual 745 points

Part Number: AM5728

Hi,

I do have a question regarding EMIF1 on AM57x8.

I'm reading the AM5728 TRM (AM572x Sitara Processors Silicon Revision 2.0, 1.1 (Rev. G)) and on the page 3348 there is a Table 15-97 "Supported Memory Types Used Together on the EMIF1 Data and ECC Buses"

From the description it seems like for DDR3 ECC is only supported with x16 data width SDRAM memories (this memory configuration is present on TI's IDK development kit).

Please confirm that ECC CANNOT be used (in any way) with x8 SDRAM memories (with configuration presented on Figure 15-44 "EMIF DDR2/DDR3 Configuration Without ECC").


Best regards,
Łukasz

  • 0
    TI__Guru**** 393215 points
    Hi,

    Please see AM572x Errata Advisory i922.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 745 points
    Hi,

    Thank you for sharing the errata document.

    However, it did not answer my question - is it possible with memory setup as on Figure 15-44 to use ECC ?

    I'm asking because the errata note mentioned that ECC works with DDR data bus size 16 and 32.
    And here is the question - on Figure 15-44 we do have single SDRAM memory data bus size equal to 8 bits, but we do have four of them which are combined to 32 bits and maps to AM5728's ddr1_d[31:0] pins.

    BR,
    Łukasz
  • 0 in reply to user4759774
    TI__Genius 9655 points

    user4759774 said:


      I'm asking because the errata note mentioned that ECC works with DDR data bus size 16 and 32.
    And here is the question - on Figure 15-44 we do have single SDRAM memory data bus size equal to 8 bits, but we do have four of them which are combined to 32 bits and maps to AM5728's ddr1_d[31:0] pins.

    BR,
    Łukasz

    The configuration you stated is valid i.e. using 4 x8 bit memory parts for creating a 32 bit parallel  bus is a valid configuration. For Adding ECC you would need another 1 x8bit memory part which is similar to the other 4 x8 memory parts. However, as Biser noted, please carefully review the Errata i922. Due to this Errata, the DDR memory access should be quanta aligned i.e. should always be a 32 bit access without any choppy bursts.
    Hope this clarifies
    Regards, Siva
  • 0 in reply to sivak
    Intellectual 745 points
    Hi,

    This clarified everything, thanks a lot.

    Best regards,
    Łukasz