RTOS: Changing AM572x pinmux configuration at runtime on M4

It is not recommended to change the pinmux in runtime for these devices due to the configuration of IO sets and delay on many of the pins. We recommend that you configure this pin statically on Linux side and then leverage this on the SLave RTOS side. There is a possibility of glitches occurring on pins if this is done during runtime operation. Hence we strongly recommend that you configure this in Uboot only and then use the pin from RTOS code on M4.

GPIO to clock which doesn`t have IO sets so you can do the following to change the nature of this pin provided you characterize the behavior of the pin and deem it safe to use.

The CTRL_CORE_PAD_XREF_CLK2 described in the TRM is used to set the pin B26 . Change the mux mode to 10 using the following code in the SOC initialization.

build settings:

define -DSOC_AM572x

Include :

#include <ti/csl/cslr_device.h>

Source:

            regVal = 0U;

           CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_WAKEUPENABLE, DISABLE);

           CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_INPUTENABLE, DISABLE);

           CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_PULLTYPESELECT, PULL_DOWN);

           CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_PULLUDENABLE, ENABLE);

           CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_MUXMODE, 0U);

           CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_MODESELECT, MUX_MODE);

           CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_DELAYMODE, 0U);

           CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_XREF_CLK2_XREF_CLK2_MUXMODE, 10U);

           ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_XREF_CLK2 = regVal;

OR

       #define HW_WR_REG32(addr, data)   *(unsigned int*)(addr) =(unsigned int)(data)

       HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_XREF_CLK2, 0x0000A);

Regards,

Rahul

PS: There are no IOSETs for these pin usecases but check your design for correct  PULL UP PULL DOWN values and configure input mode if the pin needs to be in receive mode.

All pinmux setting on this device is recommended to be done from onchip memory during initialization so please place this section of code in OCMC memory.