AM5728: GPMC problem

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Hi,

We use Ti bootloader twiked for our hardware and initialized the GPMC to communicate with the FPGA . When we run the bootloader we can see the FPGA registers and modified them as well. ==========> Please clarify the TI processor SDK RTOS release version for this problem. And which source code files in TI bootloader you used/modified to configure GPMC? What is the boot mode (MMCSD, QSPI)? Do you use TI AM572x EVM or customer board? How do you read and confirmed that the GPMC registers are untouched? From A15 memory window? C66x window?

I have some suspicion that in bootloader that you looked through A15 and MMU is disabled.

Then let say you connected the JTAG to AM57x, do you remove all the GEL files to avoid the same initilzation work already done by bootloader?

What core you connected to? A15 or C66x? Where your application intends to run? All are unclear to me.

Is your application bare metal? Or your application is SYSBIOS? Do your application enable MMU? UART_BasicExample_idkAM572x_armExampleProject enables MMU in the SYSBIOS configuration, you can't read GPMC registers directly in A15 memory window anymore if you runs this program to main(). You have to setup MMU for access. Check
e2e.ti.com/.../1989911 if help.

Also, you can look through DSP core to make sure if GMPC is really corrupted from _c_int00 to main(), or you just looked it from a wrong way because of MMU setting. Also, GPMC_REVISION register is read only, it can't be corrupted.

Regards, Eric

Hi Eric,
Here is my answers to your questions.

We use Ti bootloader twiked for our hardware and initialized the GPMC to communicate with the FPGA . When we run the bootloader we can see the FPGA registers and modified them as well. ==========> Please clarify the TI processor SDK RTOS release version for this problem. And which source code files in TI bootloader you used/modified to configure GPMC? What is the boot mode (MMCSD, QSPI)? Do you use TI AM572x EVM or customer board? How do you read and confirmed that the GPMC registers are untouched? From A15 memory window? C66x window?

Milos:
We are using one of the latest BIOS Version 6.46.2.47 and XDCTools Version 3.32.1.22 there is no source code in the Ti bootloader to initialize configure GPMC but we used Ti functions to do this.

The function is here:

void GpmcInit()
{
uint32_t retVal = 0;
uint32_t baseAddr = CSL_MPU_GPMC_CONF_REGS_REGS;
uint32_t CsTimingParam, WeOeTimingParams, RdAccTimingParams, Cyc2TimingParams;

GPMCModuleSoftReset(baseAddr) ;

do{
retVal = GPMCModuleResetStatusGet(baseAddr) ;
}while (retVal == 0) ;

/* GPMC Clock set to no idle */
GPMCIdleModeSelect(baseAddr, GPMC_IDLEMODE_NOIDLE);

/* Do not enable Auto Idle for GPMC clock */
GPMCAutoIdleConfig(baseAddr, GPMC_AUTOIDLE_FREERUN);

/* Disable interrupt from GPMC */
GPMCIntDisable(baseAddr, GPMC_FIFOEVENT_INT) ;
GPMCIntDisable(baseAddr, GPMC_TERMINALCOUNT_INT) ;
GPMCIntDisable(baseAddr, GPMC_WAIT0EDGEDETECTION_INT) ;
GPMCIntDisable(baseAddr, GPMC_WAIT1EDGEDETECTION_INT) ;

/* Disable Timout */
GPMCTimeOutFeatureConfig(baseAddr, GPMC_TIMEOUTFEATURE_DISABLE) ;

CsTimingParam = GPMC_CS_TIMING_CONFIG(
CS_DEASSERT_WR,
CS_DEASSERT_RD,
0,
0x5) ;

WeOeTimingParams = GPMC_WE_OE_TIMING_CONFIG(
WE_DEASSERT,
0x0,
WE_ASSERT,
0x0,
OE_DEASSERT,
0x0,
0x0,
OE_ASSERT) ;

RdAccTimingParams = GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(
CFG_5_RD_CYCLE_TIM,
CFG_5_WR_CYCLE_TIM,
CFG_5_RD_ACCESS_TIM,
0x0);

Cyc2TimingParams =GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(
CYC2CYC_DELAY,
GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY,
GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY,
0x0) ;


/* Cs 0 FPGA Flash */
GPMCDevTypeSelect(baseAddr,GPMC_CHIP_SELECT_0,GPMC_DEVICETYPE_NORLIKE) ;
GPMCAddrDataMuxProtocolSelect(baseAddr, GPMC_CHIP_SELECT_0,GPMC_MUXADDDATA_NOMUX ) ;
GPMCDevSizeSelect(baseAddr, GPMC_CHIP_SELECT_0, GPMC_DEVICESIZE_16BITS ) ;
GPMCDevPageLenSet(baseAddr, GPMC_CHIP_SELECT_0, GPMC_DEV_PAGELENGTH_SIXTEEN);
GPMCTimeParaGranularitySelect(baseAddr, GPMC_CHIP_SELECT_0, GPMC_TIMEPARAGRANULARITY_X1) ;
GPMCFclkDividerSelect(baseAddr, GPMC_CHIP_SELECT_0, GPMC_FCLK_DIV_BY_2) ;
GPMCCSTimingConfig(baseAddr, GPMC_CHIP_SELECT_0, CsTimingParam) ;
GPMCWEAndOETimingConfig(baseAddr, GPMC_CHIP_SELECT_0,WeOeTimingParams);
GPMCRdAccessAndCycleTimeTimingConfig(baseAddr, GPMC_CHIP_SELECT_0,RdAccTimingParams) ;
GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(baseAddr, GPMC_CHIP_SELECT_0,CFG_6_WR_ACCESS_TIM, WR_DATA_ON_ADMUX ) ;
GPMCycle2CycleAndTurnArndTimeTimingConfig(baseAddr, GPMC_CHIP_SELECT_0, Cyc2TimingParams);
GPMCWaitPinMonitoringConfig(baseAddr,GPMC_CHIP_SELECT_0,GPMC_MODE_READ, GPMC_WAITMONITORING_DISABLE) ;
GPMCWaitPinMonitoringConfig(baseAddr,GPMC_CHIP_SELECT_0,GPMC_MODE_WRITE, GPMC_WAITMONITORING_DISABLE) ;

/* Cs 1 FPGA Flash */
GPMCDevTypeSelect(baseAddr,GPMC_CHIP_SELECT_1,GPMC_DEVICETYPE_NORLIKE) ;
GPMCAddrDataMuxProtocolSelect(baseAddr, GPMC_CHIP_SELECT_1,GPMC_MUXADDDATA_NOMUX ) ;
GPMCDevSizeSelect(baseAddr, GPMC_CHIP_SELECT_1, GPMC_DEVICESIZE_16BITS ) ;
GPMCDevPageLenSet(baseAddr, GPMC_CHIP_SELECT_1, GPMC_DEV_PAGELENGTH_SIXTEEN);
GPMCTimeParaGranularitySelect(baseAddr, GPMC_CHIP_SELECT_1, GPMC_TIMEPARAGRANULARITY_X1) ;
GPMCFclkDividerSelect(baseAddr, GPMC_CHIP_SELECT_0, GPMC_FCLK_DIV_BY_2) ;
GPMCCSTimingConfig(baseAddr, GPMC_CHIP_SELECT_1, CsTimingParam) ;
GPMCWEAndOETimingConfig(baseAddr, GPMC_CHIP_SELECT_1,WeOeTimingParams);
GPMCRdAccessAndCycleTimeTimingConfig(baseAddr, GPMC_CHIP_SELECT_1,RdAccTimingParams) ;
GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(baseAddr, GPMC_CHIP_SELECT_1,CFG_6_WR_ACCESS_TIM, WR_DATA_ON_ADMUX ) ;
GPMCycle2CycleAndTurnArndTimeTimingConfig(baseAddr, GPMC_CHIP_SELECT_1, Cyc2TimingParams);
GPMCWaitPinMonitoringConfig(baseAddr,GPMC_CHIP_SELECT_1,GPMC_MODE_READ, GPMC_WAITMONITORING_DISABLE) ;
GPMCWaitPinMonitoringConfig(baseAddr,GPMC_CHIP_SELECT_1,GPMC_MODE_WRITE, GPMC_WAITMONITORING_DISABLE) ;


/*
* Map Cs 0 Address beg from 0x00000000 for FPGA Flash.
*/
GPMCCSConfig(baseAddr,GPMC_CHIP_SELECT_0,GPMC_CS_DISABLE) ; // Disable Chip Select First
GPMCMaskAddrSet(baseAddr,GPMC_CHIP_SELECT_0,GPMC_CS_SIZE_16MB ) ; // 16MB is the min size that supported .
GPMCBaseAddrSet(baseAddr,GPMC_CHIP_SELECT_0,(0x01000000 >> 24)) ; // This address is what ROM boot loader set up to.
GPMCCSConfig(baseAddr,GPMC_CHIP_SELECT_0,GPMC_CS_ENABLE) ;

/*
* Map Cs 1 Address beg from 0x00000000 for FPGA Flash.
*/
GPMCCSConfig(baseAddr,GPMC_CHIP_SELECT_1,GPMC_CS_DISABLE) ; // Disable Chip Select First
GPMCMaskAddrSet(baseAddr,GPMC_CHIP_SELECT_1,GPMC_CS_SIZE_16MB ) ; // 16MB is the min size that supported .
GPMCBaseAddrSet(baseAddr,GPMC_CHIP_SELECT_1,(0x02000000 >> 24)) ; // This address is what ROM boot loader set up to.
GPMCCSConfig(baseAddr,GPMC_CHIP_SELECT_1,GPMC_CS_ENABLE) ;
}

The boot mode QSPI.

Do you use TI AM572x EVM or customer board?
Milos:
I tested this on customer and Ti Am572x idk and the same result.


I have some suspicion that in bootloader that you looked through A15 and MMU is disabled.

Then let say you connected the JTAG to AM57x, do you remove all the GEL files to avoid the same initilzation work already done by bootloader?
Milos:
Yes we remove all the GEL files since we do all initialization in the bootloader.

What core you connected to? A15 or C66x? Where your application intends to run? All are unclear to me.
Milos:
We are connected to A15 core 0 and our application intends to run from there.

Is your application bare metal? Or your application is SYSBIOS? Do your application enable MMU?
Milos:
My Application is SYSBIOS and enables the MMU.

UART_BasicExample_idkAM572x_armExampleProject enables MMU in the SYSBIOS configuration, you can't read GPMC registers directly in A15 memory window anymore if you runs this program to main(). You have to setup MMU for access. Check
e2e.ti.com/.../1989911 if help.
Milos:
Can you please send to me correct link to check this.

Also, you can look through DSP core to make sure if GMPC is really corrupted from _c_int00 to main(), or you just looked it from a wrong way because of MMU setting. Also, GPMC_REVISION register is read only, it can't be corrupted.
Milos:
I will check this.

Regards,
Milos

Hi,

The link is https://e2e.ti.com/support/arm/sitara_arm/f/791/p/545160/1989911

Regards, Eric

Hi,
I added the part for the MMU init from the post above and now I can see the GPMC registers correctly when I stop in the main but I still could not read from the FPGA and write to the FPGA memory space 0x01000000 and 0x02000000.
What else I need to do to make this to work.
Regards,
Milos

Hi,

Good to know now you can see the GPMC configuration registers correctly from A15. Now the real problem is that GPMC doesn't work with FPGA.

Do you set up the MMU attribute for the GPMC data region? For all the GPMC registers you programed (showed in yesterday post), what code you referred to?

Regards, Eric

Hi,

As I already explain to you I could read/Write to the FPGA when I stop in the _c_init00 means the bootloader initialized the GPMC correctly and I could see the GPMC registers as well.

After adding your code in the .cfg going from _c_init00 to the main I still could see the GPMC registers but I coulld not read/write to the FPGA anymore.

Could you please send to me what I need to add to the .cfg file to fix this.

I tryed this and still did not work is this ok or I need to do something else.

var attrsFPGA1 = new Mmu.DescriptorAttrs();
Mmu.initDescAttrsMeta(attrsFPGA1);
attrsFPGA1.type = Mmu.DescriptorType_BLOCK;
attrsFPGA1.shareable = 2; // sharerable
attrsFPGA1.attrIndx = 1; // Non-cache, device memory
Mmu.setSecondLevelDescMeta(0x01000000, 0x01000000, attrsFPGA1);
Mmu.setSecondLevelDescMeta(0x02000000, 0x02000000, attrsFPGA1);

var attrsFPGA2 = new Mmu.DescriptorAttrs();
Mmu.initDescAttrsMeta(attrsFPGA2);
attrsFPGA2.type = Mmu.DescriptorType_BLOCK;
attrsFPGA2.shareable = 2; // sharerable
attrsFPGA2.attrIndx = 1; // Non-cache, device memory
Mmu.setSecondLevelDescMeta(0x02000000, 0x02000000, attrsFPGA2);
Mmu.setSecondLevelDescMeta(0x03000000, 0x03000000, attrsFPGA2);

Regards,

Milos

I added this to .cfg and I still can not read/write to the FPGA.
Can you check it is this correct.



var attrsFPGA1 = new Mmu.DescriptorAttrs();
Mmu.initDescAttrsMeta(attrsFPGA1);
attrsFPGA1.type = Mmu.DescriptorType_BLOCK;
attrsFPGA1.shareable = 2; // sharerable
attrsFPGA1.attrIndx = 1; // Non-cache, device memory
Mmu.setSecondLevelDescMeta(0x01000000, 0x01000000, attrsFPGA1);
Mmu.setSecondLevelDescMeta(0x02000000, 0x02000000, attrsFPGA1);

var attrsFPGA2 = new Mmu.DescriptorAttrs();
Mmu.initDescAttrsMeta(attrsFPGA2);
attrsFPGA2.type = Mmu.DescriptorType_BLOCK;
attrsFPGA2.shareable = 2; // sharerable
attrsFPGA2.attrIndx = 1; // Non-cache, device memory
Mmu.setSecondLevelDescMeta(0x02000000, 0x02000000, attrsFPGA2);
Mmu.setSecondLevelDescMeta(0x03000000, 0x03000000, attrsFPGA2);

Hi,

"I could read/Write to the FPGA when I stop in the _c_init00 means the bootloader initialized the GPMC correctly and I could see the GPMC registers as well."====>When you stop at _c_int00, how do you R/W FPGA? Do you have a seperate program running on other core? Can you confirm that bootloader disables cache and MMU?

"After adding your code in the .cfg going from _c_init00 to the main I still could see the GPMC registers but I coulld not read/write to the FPGA anymore." ====> can you confirm the GPMC register is the same as the point when you stop at _c_int00? That is, _c_int00 going to main() doesn't change the GPMC register?

In the .cfg file, there would be something like below to enable
// Enable the cache
Cache.enableCache = true;

// Enable the MMU (Required for L1/L2 data caching)
Mmu.enableMMU = true;

Then your added code to set memory attributes.

If you disable both (to match what you set in bootloader)
Cache.enableCache = false;
Mmu.enableMMU = false;
and remove those added code to set memory attributes. Can you see the GPMC register and be able to R/W to FPGA? If yes, you can try if cache enable caused the failure.

Regards, Eric

I just tested this and the enable cache only does not caused the failure.
Only when I enable the MMU and the Cache we have a problem.
Regards,
Milos

Hi,

Thanks for the trial! Can you let me know if you only enable MMU but disable cache, will you have this problem? Thanks very much!

Regards, Eric

I just tested option the MMU enable and the Cache disable and I still have a problem.
Regards,
Milos

Hi,
Do we have solution how to solve the Cache problem.
Please let me know.
Regards,
Milos

Hi I just tested this again and I have next code in the .cfg
var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');

// Enable the cache
Cache.enableCache = true;

// Enable the MMU (Required for L1/L2 data caching)
Mmu.enableMMU = true;

var attrs = new Mmu.DescriptorAttrs();
Mmu.initDescAttrsMeta(attrs);
attrs.type = Mmu.DescriptorType_BLOCK;
attrs.shareable = 2; // sharerable
attrs.attrIndx = 1; // Non-cache, device memory
Mmu.setSecondLevelDescMeta(0x50000000, 0x50000000, attrs);
Mmu.setSecondLevelDescMeta(0x50200000, 0x50200000, attrs);


// descriptor attribute structure
var peripheralAttrs = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(peripheralAttrs);

peripheralAttrs.type = Mmu.DescriptorType_BLOCK; // BLOCK descriptor
peripheralAttrs.noExecute = true; // not executable
peripheralAttrs.accPerm = 0; // read/write at PL1
peripheralAttrs.attrIndx = 1; // Non-cache, device memory
// MAIR0 Byte1 describes
// memory attributes for
// each BLOCK MMU entry

// Define the base address for the FPGA1
var peripheralBaseAddr = 0x01000000;

// Configure the corresponding MMU page descriptor accordingly
Mmu.setSecondLevelDescMeta(peripheralBaseAddr,
peripheralBaseAddr,
peripheralAttrs);
// Define the base address for the FPGA2
var peripheralBaseAddr = 0x02000000;

// Configure the corresponding MMU page descriptor accordingly
Mmu.setSecondLevelDescMeta(peripheralBaseAddr,
peripheralBaseAddr,
peripheralAttrs);


If I enable cache:

// Enable the cache
Cache.enableCache = true;

// Enable the MMU (Required for L1/L2 data caching)
Mmu.enableMMU = true;

I still have a problem as before I could not read/write to the FPGA.
Can you help me how to solve this problem.
Regards,
Milos

Milos, Eric,

I have a suspicion that we are using incorrect MMU module in the SYSBIOS configuration. In going over SYSBIOS documentation I noticed there are two different MMU modules: ti.sysbios.family.arm.a15.Mmu and also ti.sysbios.family.shared.vayu.Mmu. Is it possible that we should be using the "Vayu" one? Can you give it a try to see if it helps?

Michael

P.S> SYSBIOS documentation has example of configuring MMU for Vayu:

Hi Milos,

You are programming the correct MMU module (ti.sysbios.family.arm.a15.Mmu). There might be something broken with the configuration. Can you share your application's *.cfg file ?

Another quick way of determining whether the MMU is setup correctly is to use ROV to verify MMU settings. Can you try the following experiment ?

 Step 1: Disable "Run to main" from "Tools"->"Debugger Options"->"Auto Run and Launch Options" window.

 Step 2: Load the application (It should stop at _c_int00 and not run to main this time)

 Step 3: Add a breakpoint at ti_sysbios_family_arm_a15_Mmu_enableAsm__I

 Step 4: Hit run and wait for application to hit the above breakpoint. Once the breakpoint is hit, open ROV and select Mmu view. Under the level 2 tab, you can see the attributes for the memory regions you are concerned with. If they look correct then the MMU configuration is ok. Please note that the MMU rov view is a bit slow and takes time to populate. Please be patient when waiting for it to render.

Best,

Ashish

Hi Ashish,

I just followed the steps you suggested and I could not see my memory region.
There is only region for 0x40000000 and 0x80000000.

Thanks,
Milos