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AM5728: Configuring 4GB DDR3L

Heather Rysenga
Intellectual 280 points
Part Number: AM5728

We just received our custom board, and we have 4 GB of DDR3L with part number MT41K512M16HA, so there are 4 ICs total. Our problem is that Uboot/Linux only show that we have 2 GB of RAM.

Uboot works, booting into Linux works, display, ethernet, etc all work, but our memory access is limited to 2 GB.

What we're interested in doing is having Q2 access 2 GB of memory through its 1 GB window and having Q3 2 GB of memory through its 1 GB window. We want to have EMIF 1 and 2 to be interleaved on both Q2 and Q3. Do we need to set up all 4 LISA registers, or just 2 LISA registers, as seen in most examples? Does it matter which registers we use? Is this even the right way to think about this?

Is there a working example of interleaving both EMIF 1 and 2 to enable access to 4 GB of RAM?

We've looked at the DRA74x EVM uboot settings, but the register settings don't make much sense, and the settings didn't work for us. We could use some support on this.

  • 0
    TI__Guru**** 393215 points
    The software team have been notified. They will respond here.
  • 0
    TI__Guru**** 161600 points
    Hi,

    Apologies for the delayed response.
    See the following thread:
    e2e.ti.com/.../552861

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 280 points

    Hi Yordan,


    We have tried everything suggested in that and other threads. We checked that the kernel enables LPAE, verified that the higher memory interleaving was enabled in MA_PRIORITY, and we set the LISA map to enable interleaving on the lower 2 GB. I also used devmem2 to read the MA_PRIORITY register and the LISA map registers to verify they are set. The LISA map registers are set to:

        .dmm_lisa_map_0 = 0x0,
        .dmm_lisa_map_1 = 0x0,
        .dmm_lisa_map_2 = 0x80740300,
        .dmm_lisa_map_3 = 0xFF020100,
        .is_ma_present = 0x1

    Is there something we need to do in the MMU to let it know it can access a higher memory space? Or anything else we might be missing?

  • 0 in reply to Heather Rysenga
    TI__Guru**** 161600 points
    Hi,

    Ok, can you download the latest automotive processor SDK, which supports www.ti.com/.../j6evm5777. The DRA75x EVM uses 4GB RAM, 2GB on each EMIF. And the architecture of the automotive DRA75x & AM57x is quite the same, so look at the lisa map configurations there. The SDK is located here:
    processors.wiki.ti.com/.../Category:Processor_SDK_Linux_Automotive

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 280 points

    We've already looked at that SDK, and we have verified that our LISA map is the same. The LISA map is only for the lower 2 GB of memory, right? So that still doesn't help us enable the upper 2 GB. Or maybe the upper 2 GB is enabled, but U-Boot and Linux aren't aware of it because only the MPU can access it? Is there any way to determine if the MPU is able to use the upper 2 GB of RAM?

  • 0 in reply to Heather Rysenga
    Intellectual 280 points

    We found what we were missing! We went back and looked at the board file for the DRA75x EVM, and we noticed that it had a different dram_init_banksize function, which tells uboot about the second area of memory starting at 0x200000000.Here is the function in case anyone else comes looking:

    void dram_init_banksize(void)
    {
        u64 ram_size;

        ram_size = board_ti_get_emif_size();

        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
        gd->bd->bi_dram[0].size = get_effective_memsize();
        if (ram_size > CONFIG_MAX_MEM_MAPPED) {
            gd->bd->bi_dram[1].start = 0x200000000;
            gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
        }
    }

    We cheated and just set ram_size to equal 0x100000000 and changed the types of bi_dram.start/stop to u64, but maybe the more correct way would be to configure the system as a 64 bit system?

  • 0 in reply to Heather Rysenga
    Intellectual 355 points

    Another thing for a successful 4GB DDR3 configuration is to NOT enable CONFIG_ARMV7_LPAE in u-boot.  Enabling CONFIG_ARMV7_LPAE in u-boot with the dram_init_banksize update above would cause the system to "hang".  In our case, dram_init_banksize executes the following:

                gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
                gd->bd->bi_dram[0].size = get_effective_memsize();
                gd->bd->bi_dram[1].start = 0x200000000;
                gd->bd->bi_dram[1].size = CONFIG_MAX_MEM_MAPPED;   /* we defined CONFIG_MAX_MEM_MAPPED as 0x80000000 */

    Also remember to update include\asm-generic\u-boot.h to change the types of start and size to u64:

    struct {   /* RAM configuration */
      u64 start;
      u64 size;
     } bi_dram[CONFIG_NR_DRAM_BANKS];   /* we defined CONFIG_NR_DRAM_BANKS as 2 */


    The kernel DOES need CONFIG_ARM_LPAE=y for the 4GB to be recognized.

  • 0 in reply to Wilson Perez
    Intellectual 280 points

    We do have LPAE enabled in u-boot, and it hasn't caused us problems. We did also change the types of start and size in the bi_dram struct, so maybe doing that removes the problems caused by enabling LPAE?