AM3359: Internal resistors state in warm reset

Daisuke Maeda

Guru 20205 points

Part Number: AM3359
Other Parts Discussed in Thread: TMDSICE3359

Our customer wants to avoid that IOs in their board is floating during a long-term warm reset.

Is the active state of all internal pull-down/pull-up resistors warm reset insensitive?

I checked some IOs in TMDSICE3359. Each of following IOs is only connected to J3 connector in TMDSICE3359.

- UART0_CTSn (E18)
- UART0_RTSn (E17)
- UART1_RTSn (D17)
- UART1_CTSn (D18)

Each of these IOs shows logic high during a warm reset in TMDSICE3359 but is "Z" in "BALL RESET STATE" of datasheet. An active state of internal pull-down/pull-up resistors seems to maintain their current value throughout a warm reset.

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Please see Table 8-25 in the AM335x TRM Rev. O, and the notes below the table.

0 Daisuke Maeda over 8 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

Thank you for your reply.

I have already seen the notes which you pointed out. The notes will describe some Pad Control Registers are exception, i.e. warm reset in-sensitive.

I cannot find the exception details in Pad Control Registers. Which Pad Control Registers are the exception, i.e. warm reset in-sensitive?

Best regards,

Daisuke

0 Biser Gatchev-XID over 8 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

I think you misunderstand the meaning of "BALL RESET STATE" in the datasheet. In the beginning of section 4.2 this is defined as:
"6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low."

Additionally Note 25 after Table 4-1 states:
"(25) For all pins with content in the Ball Reset State column of this table, the terminal is not defined until all the supplies are ramped."

A warm reset only resets the padconf rgisters to their default value, which is "H : High-impedance with an active pullup resistor" for the pins you mention.

0 Daisuke Maeda over 8 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

Thank you for your reply.

I understand that content in "BALL RESET REL. STATE" is the default value for all pins in AM335x. Is my understanding correct?

Best regards,

Daisuke

0 Biser Gatchev-XID over 8 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

Correct.

0 Daisuke Maeda over 8 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

Thank you for your reply.

I will suggest to our customer that each of pins which are "Z" in "BALL RESET REL. STATE" is pulled up/down via an external resistor.

Best regards,

Daisuke

0 Daisuke Maeda over 8 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

I have an additional question.

The following IOs are "Z" in "BALL RESET REL. STATE".

- DDR_D[15:0]
- DDR_DQS[1:0]
- DDR_DQSn[1:0]

- USB[1:0]_CE
- USB[1:0]_VBUS
- USB[1:0]_DM
- USB[1:0]_ID
- USB[1:0]_DP

Is it allowed that these IOs are floating during a long-term warm reset?

These DDR pins not have VTT terminations since on-device terminations (ODTs) are used for these pins. During a warm reset, ODTs are disabled by DDR_ODT or DDR_RESETn driving low then these pins are floating .

These USB pins are left floating because USB is not used for our customer's boards.

Best regards,

Daisuke

0 Biser Gatchev-XID over 8 years ago in reply to Daisuke Maeda

TI__Guru**** 393215 points

Yes, these pins should be left as they are.

0 Daisuke Maeda over 8 years ago in reply to Biser Gatchev-XID

Guru 20205 points

Hi Biser-san,

Thank you for your reply.

Those pins will be left floating during a long-term warm reset to not be connected to termination resistors.

Best regards,

Daisuke

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AM3359: Internal resistors state in warm reset