Part Number: AM5728
Dear TI,
WE are setting up communications between PRU and ARM and PRU to PRU (on one ICSS)
Using the below register settings we can get the PRU to PRU communications to work (interrupt on bit 30 of R31) so one PRU can interrupt the other PRU on ICSS1 but then the rpmsg communication dies.
we have tried this before and after the rpmsg initialization and we specifically or'd our mapping in to avoid changing any rpmsg setup...
How is rpmsg setup these registers so we know how to set this up without causing a conflict.
Thanks.
volatile unsigned long * baseRegisterPtr = 0x00020000;
// Setup the interrupts
// Setup mapping of host interrupts and system interrupts
// PRUSS_INTC_HMR0 Register hex 800 = 2048
// baseRegisterPtr[2048/4] = 0x0;
// PRUSS_INTC_HMR1 Register hex 804 = 2052
baseRegisterPtr[2052/4] |= 0x00010000;
// PRUSS_INTC_CMR# Register hex 400 + (0x4*#) = 1024 + 4*#
// # = 7 in our case so 1024+4*7 = 1052
baseRegisterPtr[1052/4] |= 0x00010000;
// PRUSS_INTC_SECR0 Register hex 280 = 640 clear system interrupts 0-31
// Just clearing the used R30&31 system interrupts since all were cleared in main before
// rpmsg was initialized and set running.
baseRegisterPtr[640/4] = 0x40000000;
// PRUSS_INTC_SICR Register hex 24 = 36
// should clear channels 1 system interrupts
baseRegisterPtr[36/4] = 1;
// Enable the host and system interrupts
// PRUSS_INTC_EISR Register hex 0x28 = 40
// enable channels 1
baseRegisterPtr[40/4] = 30;
// PRUSS_INTC_HIEISR Register hex 0x34 = 52
// enable host interrupts 0 & 1
baseRegisterPtr[52/4] = 0x0;
// PRUSS_INTC_GER Register hex 0x10 = 16
baseRegisterPtr[16/4] = 0x1;