Tool/software: TI-RTOS
Hi TI,
beaglebone black, processor SDK RTOS 4.2.0.9, ccs 7.4
I am working on interrupt from PRU to ARM with beaglebone black. please find the source codes in the attachment.
On PRU side, I set __R31 = 35 in PRU_LED1.c; hopefully sending out a sys_event 19. Connection in design:
sys_event 19 --> channel 2 --> host 2 --> ARM interrupt 20 (PRU_ICSS_EVTOUT0).
I have converted the compile output of PRU_LED1.c into mydata.h for CCS7 to program beaglebone black. The program is running on PRU, which outputs the values of DDR memory, 0000000a and 0000000b also written by PRU_LED1.c.
[CortxA8] enter taskInitPRUFxn()
0x00 0000000a
0x04 0000000b
0x08 ffff0000
0x0c ffff0000
However, the interrupt never kicks in. I setup the parameters refering to other posts in this forum, as well as the examples of EtherCAT_Slave / ICSS_EMAC etc, but had difficulties to get things straight.
#define PRUSS_INTC_INITDATA { \
{ 19, 0xFF }, \
{ {19,2,1,0}, {0xFF,0xFF,0xFF,0xFF}}, \
{ {2, 2}, {0xFF,0xFF} }, \
( 4 ) \
}
PRUICSS_registerIrqHandler(handle, 0, 20, 19, 0, &PRU1Isr);
again the source programs are in the attachment. Please help to take a look
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <assert.h>
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/knl/Cache.h>
#include <xdc/runtime/Types.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/hal/Core.h>
#include <ti/csl/soc.h>
#include <ti/drv/pruss/pruicss.h>
#include <ti/drv/pruss/soc/pruicss_v1.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/board/board.h>
#include <ti/starterware/include/hw/soc_am335x.h>
#include "mydata.h"
PRUICSS_Handle handle = NULL;
uint32_t instance = PRUICCSS_INSTANCE_ONE;
extern unsigned char binBuff[8192];
#define PRUSS_INTC_INITDATA { \
{ 19, 0xFF }, \
{ {19,2,1,0}, {0xFF,0xFF,0xFF,0xFF}}, \
{ {2, 2}, {0xFF,0xFF} }, \
( 4 ) /*Enable PRU0/1, PRU_EVTOUT0/1*/ \
}
void PRU1Isr(void * ptr)
{
PRUICSS_pruClearEvent(handle,20);
System_printf("enter interrupt()\n");
}
/***********************************************************************/
/* function definitions */
/***********************************************************************/
int32_t taskInitPRUFxn(void)
{
char test[20]={0};
int i, j;
System_printf("enter taskInitPRUFxn()\n");
PRUICSS_IntcInitData pruss_intc_initdata = PRUSS_INTC_INITDATA;
PRUICSS_Config *cfg;
int32_t ret = PRUICSS_socGetInitCfg(&cfg);
if (ret != PRUICSS_RETURN_SUCCESS)
return (ret);
handle = PRUICSS_create((PRUICSS_Config*) cfg, instance);
PRUICSS_pruDisable(handle, PRUICCSS_PRU0);
PRUICSS_pruDisable(handle, PRUICCSS_PRU1);
/* Register an Interrupt Handler for an event */
ret = PRUICSS_registerIrqHandler(handle,
0,
20,
19,
0,
&PRU1Isr);
if (ret != PRUICSS_RETURN_SUCCESS)
return (ret);
// PRUICSS_setPRUBuffer(handle, PRUICCSS_PRU0, binBuff, 8192);
PRUICSS_setPRUBuffer(handle, PRUICCSS_PRU1, binBuff, 8192);
PRUICSS_pruIntcInit(handle,&pruss_intc_initdata);
PRUICSS_enableOCPMasterAccess(handle);
PRUICSS_pruExecProgram(handle, PRUICCSS_PRU1);
PRUICSS_pruEnable(handle, PRUICCSS_PRU1);
memcpy((unsigned char*)test, (unsigned char*)(0x80000000),20);
System_printf("\n");
for (i=0;i<5;i++)
{
System_printf("\n0x%02x\t", i*4);
for (j=3;j>=0;j--)
System_printf("%02x", test[i*4+j]);
}
while(1)
{
}
return 0;
}
/*
* ======== main ========
*/
int main()
{
Error_Block eb;
int32_t ret = -1;
Error_init(&eb);
Board_initCfg cfg = BOARD_INIT_PLL| BOARD_INIT_MODULE_CLOCK | BOARD_INIT_DDR | BOARD_INIT_ICSS_PINMUX | BOARD_INIT_UART_STDIO | BOARD_INIT_ICSS_ETH_PHY;
ret = Board_init(cfg);
if (ret != BOARD_SOK)
{
System_printf("main: Board_init returned error code: %d\n", ret);
return -2;
}
taskInitPRUFxn();
BIOS_start();
return(0);
}
/*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_intc.h>
#include <pru_ctrl.h>
#include "resource_table_empty.h"
volatile register uint32_t __R30;
volatile register uint32_t __R31;
/* Mapping Constant table register to variable */
volatile far uint32_t CT_DDR __attribute__((cregister("DDR", near), peripheral));
/* PRU-to-ARM interrupt */
#define PRU0_ARM_INTERRUPT (19+16)
#define HOST_NUM 2
#define CHAN_NUM 2
void main(void)
{
uint32_t *pDdr = (uint32_t *) &CT_DDR;
/* Clear any pending PRU-generated events */
__R31 = 0x00000000;
/* Start preparing message for host - make sure it's not 0xB */
pDdr[1] = 0x0001;
__R31 = 35;
/* Ensure CT_DDR (C31) is pointing to start of DDR memory (0x80000000) */
PRU0_CTRL.CTPPR1_bit.C31_BLK_POINTER = 0x0;
/* Write value of 0xB which Host will read after receiving the interrupt */
pDdr[0] = 0xA;
pDdr[1] = 0xB;
/* Halt the PRU */
__halt();
}
/**
* @file UART_soc.c
*
* @brief This file defines the UART interface structure specific to AM335x
*/
/*
* Copyright (c) 2014-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================*/
#include <ti/csl/csl_utils.h>
#include <ti/drv/uart/UART.h>
#include <ti/starterware/include/types.h>
#include <ti/starterware/include/hw/soc_am335x.h>
#include <ti/drv/uart/src/v1/UART_v1.h>
#define CSL_UART_PER_CNT (6U)
#define CSL_EDMA3_CHA_UART0_RX (27U)
#define CSL_EDMA3_CHA_UART0_TX (26U)
#define CSL_EDMA3_CHA_UART1_RX (29U)
#define CSL_EDMA3_CHA_UART1_TX (28U)
#define CSL_EDMA3_CHA_UART2_RX (31U)
#define CSL_EDMA3_CHA_UART2_TX (30U)
#define CSL_EDMA3_CHA_UART3_RX (8U) /* Cross bar mapped */
#define CSL_EDMA3_CHA_UART3_TX (7U) /* Cross bar mapped */
#define CSL_EDMA3_CHA_UART4_RX (10U) /* Cross bar mapped */
#define CSL_EDMA3_CHA_UART4_TX (9U) /* Cross bar mapped */
#define CSL_EDMA3_CHA_UART5_RX (12U) /* Cross bar mapped */
#define CSL_EDMA3_CHA_UART5_TX (11U) /* Cross bar mapped */
/* UART configuration structure */
UART_HwAttrs uartInitCfg[CSL_UART_PER_CNT] =
{
{
SOC_UART_0_REGS,
72,
0,
48000000U,
CSL_EDMA3_CHA_UART0_RX,
CSL_EDMA3_CHA_UART0_TX,
0,
0,
0,
0,
0,
NULL,
UART_RXTRIGLVL_8,
UART_TXTRIGLVL_56,
TRUE, /* default DMA mode */
FALSE, /* Loopback disabled by default */
TRUE, /* Interrupt enabled by default */
},
{
SOC_UART_1_REGS,
105,
0,
48000000U,
CSL_EDMA3_CHA_UART1_RX,
CSL_EDMA3_CHA_UART1_TX,
0,
0,
0,
0,
0,
NULL,
UART_RXTRIGLVL_8,
UART_TXTRIGLVL_56,
TRUE, /* default DMA mode */
FALSE, /* Loopback disabled by default */
TRUE, /* Interrupt enabled by default */
},
{
SOC_UART_2_REGS,
106,
69,
48000000U,
CSL_EDMA3_CHA_UART2_RX,
CSL_EDMA3_CHA_UART2_TX,
0,
0,
0,
0,
0,
NULL,
UART_RXTRIGLVL_8,
UART_TXTRIGLVL_56,
TRUE, /* default DMA mode */
FALSE, /* Loopback disabled by default */
TRUE, /* Interrupt enabled by default */
},
{
SOC_UART_3_REGS,
44,
0,
48000000U,
CSL_EDMA3_CHA_UART3_RX,
CSL_EDMA3_CHA_UART3_TX,
0,
0,
0,
0,
0,
NULL,
UART_RXTRIGLVL_8,
UART_TXTRIGLVL_56,
TRUE, /* default DMA mode */
FALSE, /* Loopback disabled by default */
TRUE, /* Interrupt enabled by default */
},
{
SOC_UART_4_REGS,
137,
0,
48000000U,
CSL_EDMA3_CHA_UART4_RX,
CSL_EDMA3_CHA_UART4_TX,
0,
0,
0,
0,
0,
NULL,
UART_RXTRIGLVL_8,
UART_TXTRIGLVL_56,
TRUE, /* default DMA mode */
FALSE, /* Loopback disabled by default */
TRUE, /* Interrupt enabled by default */
},
{
SOC_UART_5_REGS,
138,
0,
48000000U,
CSL_EDMA3_CHA_UART5_RX,
CSL_EDMA3_CHA_UART5_TX,
0,
0,
0,
0,
0,
NULL,
UART_RXTRIGLVL_8,
UART_TXTRIGLVL_56,
TRUE, /* default DMA mode */
FALSE, /* Loopback disabled by default */
TRUE, /* Interrupt enabled by default */
},
};
/* UART objects */
UART_V1_Object UartObjects[CSL_UART_PER_CNT];
/* UART configuration structure */
CSL_PUBLIC_CONST UART_config_list UART_config = {
{
&UART_FxnTable_v1,
&UartObjects[0],
&uartInitCfg[0]
},
{
&UART_FxnTable_v1,
&UartObjects[1],
&uartInitCfg[1]
},
{
&UART_FxnTable_v1,
&UartObjects[2],
&uartInitCfg[2]
},
{
&UART_FxnTable_v1,
&UartObjects[3],
&uartInitCfg[3]
},
{
&UART_FxnTable_v1,
&UartObjects[4],
&uartInitCfg[4]
},
{
&UART_FxnTable_v1,
&UartObjects[5],
&uartInitCfg[5]
},
/* pad to full predefined length of array */
{NULL, NULL, NULL},
{NULL, NULL, NULL},
{NULL, NULL, NULL},
{NULL, NULL, NULL},
{NULL, NULL, NULL}
};
/**
* \brief This API gets the SoC level of UART intial configuration
*
* \param index UART instance index.
* \param cfg Pointer to UART SOC initial config.
*
* \return 0 success: -1: error
*
*/
int32_t UART_socGetInitCfg(uint32_t index, UART_HwAttrs *cfg)
{
int32_t ret = 0;
if (index < CSL_UART_PER_CNT)
{
*cfg = uartInitCfg[index];
}
else
{
ret = -1;
}
return ret;
}
/**
* \brief This API sets the SoC level of UART intial configuration
*
* \param index UART instance index.
* \param cfg Pointer to UART SOC initial config.
*
* \return 0 success: -1: error
*
*/
int32_t UART_socSetInitCfg(uint32_t index, const UART_HwAttrs *cfg)
{
int32_t ret = 0;
if (index < CSL_UART_PER_CNT)
{
uartInitCfg[index] = *cfg;
}
else
{
ret = -1;
}
return ret;
}
Mike
