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AM4379: Peripheral PLL not locking

Christof Vogt
Prodigy 30 points
Part Number: AM4379

Hello,

we have developed a board with the AM4379 simliar to the AM437x IDK.

At the moment I am only working with the gel scripts for initalization. They are based on the AM437x scripts for the IDK board. If I connect to the Cortex A9 the Script is hanging on the configuration of the Periphery PLL.

The Outout:
CortexA9: Output:  **** Device Type: GP
CortexA9: GEL Output: System input clock is 24MHz
CortexA9: GEL Output: ****  AM43xx OPP100 with CLKIN=24MHz is in progress .........
CortexA9: GEL Output:      ****  Going to Bypass...
CortexA9: GEL Output:      ****  Bypassed, changing values...
CortexA9: Output:      ****  Locking PLL
CortexA9: GEL Output:      ****  MPU PLL locked
CortexA9: GEL Output:      ****  Core Bypassed
CortexA9: GEL Output:      ****  Now locking Core...
CortexA9: GEL Output:      ****  Core locked
CortexA9: GEL Output:      ****  Calculated PER SD Divisor=4
CortexA9: GEL Output:      ****  PER DPLL Bypassed

The PLL is configured with the command PER_PLL_Config(  CLKIN, 9, 400, 5); If I comment out the PER_PLL all other PLLs are working well. DDR3 is also running correct. I have routet the other PLLs to CLKOUT and measured them. All frequencies are correct. Only PER_PLL will not lock and stay in bypass mode.

This is the register dump after I canceled the hanging gel script. The PLL should lock, but ST_DPLL_CLK Bit is not set.

I have already checked the supply Pins (VDDA1P8V_USB0). The voltage is 1.8 V, and there are capacitors near the pins.

I am not sure how I can debug this issue. Are there other Pins I can check or some registers where I can see which part is not working?

Best regards,

Christof Vogt

  • 0
    TI__Guru**** 393215 points
    Hi,

    Have you checked the VDDA1P8V_USB0 supply for noise? See section 5.13.2.1.1 of the AM437x Datasheet Rev. D for details.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 30 points
    Hi,

    we have double checked our supplies. We measured them and also compared with the other PLL supplies. They are looking good and are in the Range of the referenced datasheet.

    Best Regards
  • 0 in reply to Christof Vogt
    TI__Guru* 87040 points
    Hi Christof,
    Do you see this issue across multiple boards?
    It is good that you checked the supplies, which is typically the problem with the scenario you describe. Since that looks OK, could it possibly be an assembly issue (power/ground pins not properly soldered for the PER power rail)? If you can check multiple boards, this can confirm or eliminate that possiblity.
    Also, ensure there are no droops on VDDA1P8V_USB0 around the time the PLL is trying to lock.

    Regards,
    James Doublesin
  • 0 in reply to JJD
    Prodigy 30 points

    Hi James,

    thank you for your response.

    Before your answer I already tried 3 Boards. All have the same issue. Now I tried 2 more and they are running. Seems that there is some production issue.

    I'm not sure if on the first power on the SYSBOOT was configured correctly (initially all  values are high). On the running one they were corectly configured on the first power on. Is it possible that this damage something?

    Thank your for the assistance.

    Best regards

  • 0 in reply to Christof Vogt
    TI__Guru* 87040 points
    Hi Christof, it is tough to know if a SYSBOOT of all ones will damage the part, but i wouldn't rule it out. There are some reserved sysboot signals that need to be low for normal operation.
    On the non working boards, ensure that the SYSBOOT is configured correctly and double check it by checkout the CONTROL_STATUS register (0x44E10040). This will show what the processor latched in for SYSBOOT. If that looks good and if the PLL still fails to lock, try soldering on new devices.

    Regards,
    James