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CCS/AM5716: IPU Unicache prefetch issue

Part Number: AM5716

Tool/software: Code Composer Studio

Hello,

I am trying the Prefech of UNICACHE.  After enabling CACHE_OCP[4]Prefetch, however, it spends around 1200 more CPU cycles (2100 -> 3300). I suppose that the Prefetch doesn't help but increases the bus traffic!? Do I misuse Prefetch? Can you provide a experiment to help me test Prefetch of UNICACHE?

The following is my pseudo code. 

#define SIZE (65536)     // 64*1024
#define STRIDE (32)     // 256/8

char a[SIZE];

j = a[STRIDE*0];
j = a[STRIDE*1];
j = a[STRIDE*2];
j = a[STRIDE*3];
j = a[STRIDE*4];
j = a[STRIDE*5];
j = a[STRIDE*6];
j = a[STRIDE*7];
j = a[STRIDE*8];
j = a[STRIDE*9];
j = a[STRIDE*10];
j = a[STRIDE*11];
j = a[STRIDE*12];
j = a[STRIDE*13];
j = a[STRIDE*14];
j = a[STRIDE*15];

Regards,

Hungwei

  • The RTOS team have been notified. They will respond here.
  • Hungwei,

    Please take a look at the following app note on how we measure the impact of different Cache policy on CPU performance. the test case defined are provide in source and perform a memory copy, memory read and memory write from different memory.

    www.ti.com/.../sprac46.pdf

    Prefetching in your case may be causing higher latency since you are forcing prefetch on every transaction even when the data is already in L1 cache.

    Regards,
    Rahul
  • Hello Rahul,

    Thanks! I m reading the document you provide. But it seems this document doesn't mention any performance improvement by prefetch of UNICACHE?

    >Prefetching in your case may be causing higher latency since you are forcing prefetch on every transaction even when the data is already in L1 cache.

    I don't want to prefetch the data which is already in UNICACHE, so I should set the registers as following?

    - CACHE_OCP[4]PREFETCH : 0x0

    - CACHE_MMU_LARGE_POLICY_i[6]Preload : 0x1

    Do you provide any document about the prefetch mechanism? For example, the prefetch distance and stride size.

    Regards,
    Hungwei