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TLV320AIC3268: Clock Settings, DSP Slave

Part Number: TLV320AIC3268

Folks,

I have been battling this for days now and don't have a resolution.

The TLV320 is being used in slave mode. It is a slave to the MCLK, WCLK, and BCLK. The DSP is expected to output audio content at the BCLK on the DOUT1 channel.

The sample rate of the audio is 48kHz or 44.1kHz. The master will adjust the MCLK accordingly where clock equals fs * 256 and BCLK is fs * 64  The WCLK (LRCLK) equates to the sample rate.

Can you tell me what the appropriate settings are within the DSP to make this happen without any noise?

Regards,

Phil