TAS5825M: Startup Procedures with continued I2S output clock

Hi Team

From datasheet: 7.5.3.1 Startup Procedures
3. Once power supplies are stable, bring up PDN to High and wait 5ms at least, then start SCLK, LRCLK.
// my question: Whether it will be a problem  if there is continued I2S output clock(SCLK/LRCLK) at the beginning of the system's power-on,
that is to say, the SCLK LRCLK start eariler than /PDN.