Hi Team,
In the EE table for ADC gain error, the typical spec is 0.82dB with a 0-dB PGA gain setting. However, in Table 9, for the 0-dB setting, the typical gain error is around 0.52dB. Therefore, is this a typo in the EE table?
Thanks,
Jared
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Hi Team,
In the EE table for ADC gain error, the typical spec is 0.82dB with a 0-dB PGA gain setting. However, in Table 9, for the 0-dB setting, the typical gain error is around 0.52dB. Therefore, is this a typo in the EE table?
Thanks,
Jared
Hi Jared,
The gain error spec in the EC table is stated as a typical value and varies from device to device. I believe the reason for using the .82dB gain error typical value was to give some margin.
Regards,
Aaron Estrada
Hi Aaron,
So sorry, not Table 9, I meant Figure 9. In Figure 9 below (which I believe is for typical values), at 0dB for the PGA setting, the gain error looks to be around0.52dB (red circle), while a gain setting of around 60dB points to a gain error of around 0.82dB

So for Figure 9 and the EE table to match each other, shouldn't either the test conditions change to say 60dB PGA setting or the spec for the test conditions below be 0.52dB?

Best,
Jared
Hi Jared,
Apologies for the delay here.
Looking at Figure 9, you can see that ~0.82dB is there at max PGA gain. Since the typical spec in the Electrical Characteristics table has a value of 0.82dB, we suspect that this was spec'd to add some guard room.
Regards,
Aaron Estrada
Hi Aaron,
Thanks for the feedback. However, can we agree that the EE table should specify the test conditions for for PGA setting of 59.5dB? Figure 9 and the EE table simply do not align in what they have specified, even if margin is being built in.
Thanks,
Jared
Hi Jared,
I agree with you. I am sure this could have been labeled better as it is a bit confusing. I have made note of this.
Regards,
Aaron Estrada