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TLV320AIC3106: Question of TLV320AIC3106 Out-of-Band Noise of Microphone ADC

Wayne Chen (Audio AE)
Genius 15950 points
Part Number: TLV320AIC3106


Hi Sirs,

My customer encounters a noise floor problem with the AIC3106's Microphone ADC input. We can see spikes within audible band, the FFT plots was captured from recorded data stream from I2S.  
Are those noise spikes harmonic components of Out-of-Band noise? Can we reduce those noise energy including 60Hz by I2C configurations?



Thank you and Best regards,

Wayne Chen
05/27/2021

  • 0
    TI__Mastermind 22950 points

    Hello Wayne Chen,

    Was there any input applied to the device during this measurement?

    We generally see a flat response with the exception of some possible idle tones. As an example, I have attached an FFT of the AIC3107. This is a device in the same family and I would expect the AIC3106 to behave similarly. This FFT was taken with a lot of averaging to show idle tones. You can see them present but their magnitude is rather small. 

    Because the customer is seeing some spurious tones inside the audio band, I would like to check that the device is properly configured. Can the customer please provide an I2C dump of the device configuration as well as some clock information? MCLK, BCLK, WCLK values and the desired Fs would be helpful. If using the AP to send the clocks, a screenshot of the digital serial settings can be provided. 

    Regards,

    Aaron Estrada

  • 0 in reply to Aaron Estrada
    TI__Genius 15950 points

    Hello Aaron,

    Thank you for your concern. Attached file is customer's I2C dump data. Please review them and inform us if you need addition information for trouble shooting.

    Here are CLK configurations on customer's system board. Schematic and PCB board file were sent by Email,

    LRCK   MCLK          BCLK
    --------------------------------------------
    8KHz    3.075MHz    512KHZ
    16KHz  3.075MHz    1.025MHZ
    48KHz  24.5MHz      3.072MHz
    --------------------------------------------

    Thank you and Best regards,

    Wayne Chen
    06/01/2021

    Fullscreen i2c-dump-aic3106.txt Download 
    # i2cdump -f -y  4 0x18 b
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: 00 00 00 10 04 00 00 00 00 00 00 01 00 00 00 80
10: 80 ff ff 78 78 78 78 78 78 06 00 fe 00 00 fe 00
20: 00 00 00 00 00 00 00 00 00 00 00 80 80 00 00 00
30: 00 00 00 04 00 00 00 00 00 00 04 00 00 00 00 00
40: 00 04 00 00 00 00 00 00 04 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 10 04 00 00 00 00 00 00 01 00 00 00 80
90: 80 ff ff 78 78 78 78 78 78 06 00 fe 00 00 fe 00
a0: 00 00 00 00 00 00 00 00 00 00 00 80 80 00 00 00
b0: 00 00 00 04 00 00 00 00 00 00 04 00 00 00 00 00
c0: 00 04 00 00 00 00 00 00 04 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
#

  • +1 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 22950 points

    Hi Wayne,

    It looks like the PLL/clocks are configured incorrectly. Using the 48kHz Fs as an example, the PLL is not needed but clock coefficient Q needs to be set to 4. This will divide 24.5MHz (I am assuming it is a 24.576MHz clock) down to 48kHz Fsref. Register 2 is then used to obtain the desired Fs from Fsref.

    So 16kHz and 8kHz Fs can all come from the same 24.5MHz clock. There is no need to change this. The customer would just need to use register 2 and set it to Fsref/3 for 16kHz and Fsref/6 for 8kHz. 

    Moving forward, please ask the customer to use the 24.5MHz MCLK and set Page 0, Register 3 to 0x20 and Page 0, Register 2 according to what sample rate is needed. I hope this helps.

    Regards,

    Aaron Estrada

  • 0 in reply to Aaron Estrada
    TI__Genius 15950 points

    Hello Aaron,

    Would you please review customer's configuration with fixed MCLK of 3.072MHz as an input to TLV320AIC3106?

    FSREF = 48 KHz
    P = 1
    R = 1
    J = 32
    D = 0
    Q = 2

    Register 0x02 value varies with sample rate, if playing audio of
    a) 16KHz : Register value is 0x44, which results in clock setting to fsref/3 (16KHz)
    b) 8KHz : Register value is 0xaa, which results in clock setting to fsref/6 (8KHz)

    Thank you and Best regards,

    Wayne Chen
    06/04/2021

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 22950 points

    Hi Wayne,

    Those PLL coefficients look good and follow what is recommended in the data sheet. Is the customer still seeing these tones with the above coefficients?

    Regards,

    Aaron Estrada

  • 0 in reply to Aaron Estrada
    TI__Genius 15950 points

    Hello Aaron,

    Customer keeps seeing noise spur problem with the PLL setting. Is it related to schematic and layout?

    Thank you and Best regards,

    Wayne Chen
    06/07/2021
     

  • 0 in reply to Wayne Chen (Audio AE)
    TI__Mastermind 22950 points

    Hi Wayne,

    As I mentioned offline, I will take a look at the layout. 

    Regards,

    Aaron Estrada