• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 290 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC24K: Minimum Clk to output delay and Maximum Setup and Hold time are not given in Datasheet. What to consider?

Deepeshwar Kumar
Prodigy 40 points
Part Number: TLV320AIC24K
Other Parts Discussed in Thread: TLV320DAC32

Hi TI,

I need one help regarding the timing constraints given for the Serial communication of TLV320AIC24K. Here minimum time for Delay time, SCLK↑ to FS/FSD↓ is not given. Also for Delay time, SCLK↑ to FS/FSD↑ not given. Similarly, maximum Setup time, DIN, before SCLK↓ , and maximum Hold time, DIN, after SCLK↓ are not given in the datasheet. What value we need to consider for them, can you please clarify this missing information? We need this information to add a timing constraint for FPGA. I have attached a timing information image for reference. 

Regards,

Deepeshwar

  • 0
    TI__Guru** 109695 points

    Hi Deepeshwar,

    This device is considerably old, this may be the reason it is not fully specified like more moderns devices. I would say you can use the same timing schemes as other devices like TLV320DAC32.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators