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Original question:

TLV320AIC3262: How to Enable ASRC Function in TLV320AIC3262

TLV320AIC3262: Use of App8x4xArbiter framework and miniDSP A to miniDSP D interconnection

Xavier Gigandet
Prodigy 10 points
Part Number: TLV320AIC3262


Hi,

It seems that when selecting the App8x4xArbiter framework for TLV320AIC3262 in PurePath Studio, the interprocessor library is empty. Does that mean that this framework cannot support interconnections between miniDSP A and miniDSP D?

I would like to route the following:

- [ASI1 (I2S, mono, 16kHz)] -> Left DAC

- [ASI2 (I2S, stereo, 48kHz) mono downmix] + [ADC right] -> Right DAC

My understanding is that the ASRC - required to handle the two different sampling rates of the ASI1 and ASI2 - is only available in the App8x4xArbiter framework. But then, since the interprocessor library is empty, I do not find a way to route the ADC to the DAC (through miniDSP). Is there any other way to handle this particular usecase?

  • +1
    TI__Mastermind 23050 points

    Hi Xavier,

    The ASRC block only exists in the DAC DSP and like you mentioned it's not possible to pass data between the miniDSPs when this function is used.

    The way the ASRC works is it mixes the down/upsampled data on one of the ASI ports with the data from the other before outputting to the DAC, so all of the DAC output data ends up at the same sample rate. 

    I'm not sure if what you want to do is possible, but you might try physically routing the ADC DOUT on ASI1 to one of the DIN pins on ASI1 and then use the other DIN pin for your 16kHz mono I2S. This assumes you are also running the ADC at 16kHz though. The flow might look something like this and you would need to set up the ASI registers to operate with multi-lane I2S. 

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Prodigy 10 points

    Hi Zak,

    Thanks for your answer, looks like a good idea! I will probably consider another alternative in our architecture, where the ASRC would be managed by another processor, so that the codec can operate at a single rate of 48kHz. I will keep your proposal as alternative if it turns out it is not feasible.

    Thanks,

    Xavier