• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 30 subscribers
  • Views 334 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3101: Input signal level

Yasushi Fujiwara
Genius 12725 points
Part Number: TLV320AIC3101

Hello Experts,

Customer measured the input signal level at EVM. The result was 0.610Vrms(-2.076dBu) at 0dBFS. Customer would like to know the variation of the input signal level. (The datasheet stated 0.707Vrms(single-ended. Customer mentioned that 0.61Vrms is lower than their expectation.)
[conditions]
- input: JP8(0dBFS)
- measurement point: TP7(JP3/4 are open.)
- preset(GUI): Differential Input to Digital Output

Best Regards,
Fujiwara

  • 0 in reply to Sanjay Dixit
    TI__Mastermind 23030 points

    Can you please send me the part number of the evm or any documentation you might have. I cant locate JP3,JP8 on the documentation that is there on the Internet

  • 0 in reply to Sanjay Dixit
    TI__Genius 12725 points

    Hello Sanjay-san,

    Please see below user guide. (p38 EVM schematic) I'm sorry, JP3/4 and JP8 are typo. Correct name is JMP3/JMP4 and J8.
    https://www.tij.co.jp/jp/lit/ug/slau219a/slau219a.pdf?ts=1626826557002&ref_url=https%253A%252F%252Fwww.tij.co.jp%252Fproduct%252Fjp%252FTLV320AIC3101

    Customer mentioned that customer measured their board and got almost same result.

    B    est Regards,
    Fujiwara

  • 0 in reply to Yasushi Fujiwara
    TI__Mastermind 23030 points

    The input is given at IN2. 0.7Vrms should correspond to 0dbFS.

    There is an individual attenuator as well as a PGA in the signal path before the signal reaches the ADC. For this test both components need to be set to 0db.

    If you refer to figure 15 on page 9 of the part datasheet you can see that the PGA has a gain error of as much as 0.55db at 0db PGA Gain . This corresponds to a change in gain of about 6% for the PGA.  Thus a gain of 1 in the PGA may in fact be as High  as 1.06 .  This means that .7/1.06 or 0.66v signal at input may result in full scale value.

    I think we need to be sure that The gain of the input attenuators as well as the PGA is set to 0db for this test.

    Therefore I list some I2C Values for this purpose. Perhaps you could try the test once again after changing these values.

    Register   Value

    15             0x00         PGA Gain Left 

    16             0x00         PGA Gain Right

    17             0x0F

    18             0XF0

    19             0X7C

    21              0X78

    22              0X7C

    24              0X78

  • 0 in reply to Sanjay Dixit
    TI__Genius 12725 points

    Hi Sanjay-san,

    Thank you for reply.

    Customer is using the preset register settings as I mentioned below.
    => preset configuration Tab in TPA310x EVM GUI : ADC = Differential Input to Digital Output.

    I believe that the PGA gain of preset register settings is set "0dB" in preset of GUI. Please confirm about register settings of the above preset.

    And please tell a variation of the input signal level at 0dBFS of Digital output. If it does not have much variation, where portion have a gain? ADC itself or other block? You mentioned that PGA have gain variation typically 0.5dB, but customer measurement result is about -2dB from the spec(0.7Vrms typ). So I think there is an another gain in signal path between IN2L/R(14/16pin) and DOUT(5pin).

    Best Regards,
    Fujiwara

  • 0 in reply to Yasushi Fujiwara
    TI__Mastermind 23030 points

    Please refer tp page 7. The Datasheet gives in the electrical specifications a Gain error of 0.82 db at -2db FS  . This should account for errors in PGA and input attenuator. This is a Typical value and in practice the actual value can be higher and 1db may not be uncommon. 

    With 0.7v  a 1 db error results in 0.7/1.12 or 0.625v which is close to what the customer reads.

    These tests are typically conducted at a level lower then 0dbFS.  The customer should conduct the test at maybe half signal level and check how much the gain deviates from the theoretical value. A gain error in the range of 1 db would be as expected