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TAS5825P: If audio clock is given when PDN is enable, what will happen?

Dai
Intellectual 270 points
Part Number: TAS5825P

Hello,


https://www.tij.co.jp/lit/ds/symlink/tas5825p.pdf?ts=1627548293131&ref_url=https%253A%252F%252Fwww.tij.co.jp%252Fproduct%252Fjp%252FTAS5825P%253Fqgpn%253Dtas5825p

Regarding datasheet P43, startup procedure(9.5.3.1)

> Once power supplies are stable, bring up PDN to High, then start SCLK, LRCLK.

If Host device gives SCLK and LRCK before bring up the PDN to High, what will happen?
(PDN brought up to high after given both clocks.)

  • +1
    TI__Mastermind 49580 points

    Hi Dai

         To pull PDN "High" and wait for 5ms can guarantee the internal 1.5V voltage to be stable. With this internal 1.5V, the digit core can get ready for signals and will go into Hi-Z state by default. 

         To bring up the PDN high first, it's like send the signal to a chip's IO pin without power up the chip first. Of course there's no danger at most of the times, but it's not a 100% guarantee. Consider it as a potential risk.

         Thank you.