TLV320ADC6140: TDM slot 0 not being clocked out when TX_FILL set to Hi-Z

Hello,

I will take a closer look at this and respond within 24 hours,

Best Regards,

Carson

Hello,

After taking a closer looking I am confused of what you are considering to be slot 0?

And why is your FSYNC low time so large?

FSYNC should be low only for a cycle or a small integer multiple of BLCK

And what kind of data out were you expecting for a Hi-Z output?

Best Regards,

Carson

Hello Carson,

Slot 0 occurs at the falling edge of FSYNC in the above figures and I've set the FSYNC polarity to inverted in the ADC via the FSYNC_POL bit in the ASI_CFG0 register since the rising edge of FSYNC starts the data transfer in TDM mode. I referred to section 8.3.1.2.1 of the TLV320ADC6140 data sheet (SBAS992A –JULY 2019–REVISED OCTOBER 2019).

FSYNC and BCLK are generated by the processor that I am using. The FSYNC low time is 32 multiples of BCLK.

I referred to section 3.1 ASI Configuration for Shared TDM of "Multiple TLV320ADCx140 Devices with Shared TDM and I2C Bus" (SBAA383B–April 2019–Revised January 2020) for the Hi-Z setting. According to this application report, "This configuration requires that all the devices place their outputs in high-impedance mode, so another device can drive the bus." I did this via the TX_FILL bit of ASI_CFG0. I have two ADCs sharing the bus.

I don't understand why the data is clocked out properly when TX_FILL = 0 (transmit 0 for unused cycles) but not when TX_FILL = 1 (use Hi-Z for unused cycles).

Thank you for your responses so far.

Regards,

Sandra

Hi Sandra,

So your saying other ADC data isnt driving dataline when TX_FILL = HI-Z but is when it is set to transmit 0.

-Carson

Also is there a pull-up on the line?

Hello Sandra,

Can you confirm that in first graph that it is not slot 0 that outputs after FSYNC rising edge?

I am not 100% sure but I do believe reversing FSYNC polarity does not mean the that data starts on falling edge.

Best Regards,

Carson

Hi Carson,

In the first graph above, it is slot 1, not slot 0, that is output after the FSYNC rising edge.

I hope the following PDF explains things better. I have both ADCs enabled and their SDOUT inputs tied together as I need all eight channels, four per ADC, recorded.

TI forum response.pdf

Regards,

Sandra

Quick question, 

It says you are using normal polarity in last graph but does not reflect that in recording?

Hi Carson,

The plots show FSYNC and BCLK as generated by my processor. I have the ADCs set to slave mode where FSYNC and BCLK are inputs to the ADCs. My processor starts recording at the falling edge of FSYNC.

I'm going by section 8.3.1.2 of the data sheet, "The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using the FSYNC_POL" and "In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order." My understanding is that the FSYNC_POL bit tells the ADC to use either the default polarity (rising edge in the case of TDM) or inverted polarity (falling edge in the case of TDM). As my processor starts on the falling edge, I used inverted polarity in the TDM case. I didn't need to invert the polarity in the I2S case because I2S starts on the falling edge anyway.

It's only when the ASI data output for unused cycles is set to Hi-Z in TDM mode that the slot 0 data is not clocked out. The data is clocked out in TDM mode when the output is set to 0 for unused cycles. Both settings for unused cycles work in I2S mode. I need to use the Hi-Z output option because I need to share the audio bus between two ADCs.

Regards,

Sandra

Hello Sandra,

If you still want to use Hi-Z can you adjust by reducing the low time of FSYNC to 1 or 2 cycles then add a TX_OFFSET. This seems to be some bug where some large capacitance is trying to be filled when HI-Z is implemented and your FSYNC is low, if you can just minimize FSYNC low time and add offset this issue should not occur.

Would that be acceptable for you?

Best Regards,

Carson