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PCM4202: Relation between audio data width and BCK clock, and other data format questions

Part Number: PCM4202
Other Parts Discussed in Thread: PCM1804

Hello team,

I received a question from the customer about audio data format of PCM4202.

① Relation between audio data width and BCK clock

When the PCM4202 is set to PCM Slave mode, does the width of the 1-bit audio data output depend on the clock of the BCK that is supplied externally to the PCM4202?

For example: If BCK is 64FS when FS=48kHz, the BCK's 1-bit width is set to 1/64FS[s]; if BCK is 128FS, the 1-bit width is set to 1/128FS[s].

② Confirm of what frequency should be entered to BCK

When the PCM4202 was set to PCM Slave mode and Single Rate Sampling mode, the data sheet was written to enter 128FS in the BCK. Would you confirm if this is correct? (Datasheet p16)

With other ADCs, they have seen BCK set to 64FS well, and they have never seen an ADC set to 128FS, so I want to check it just in case.

③ Data format difference between function compatible devices

The PCM4202 is a function compatible product of the PCM1804 pin-control, but there is a difference in the data format when the audio data is at the PCM output.

When set to 24bit Left Justified, the PCM4202 is left justified from the MSB, while the PCM1804 is left justified from the LSB.

Is it convenient to recognize that there are differences in data formats even in functional-compatible products?

Please contact us if there are more information needed.

Best Regards,

Ryotaro Fukui

  • Hello,

    The data bit width is determined by what BCK is, whatever period of BCK is the data bit width. The setting of the ratio in slave mode is just having device know what BCK you are putting into it, it is not determining anything do with data width. 

    Yes 128FS would be proper and so then in slave mode they would need to provide a BCK clock that 128xFs frequency

    Answer to 3rd question is more dependent on where the data is being sent and whatever device is receiving it has a certain setting for receiving MSB or LSB and if it can be changed.

    Best Regards,

    Carson

    Low Power Audio Applications

  • Hello,

    Sorry for the late reply.

    Thank you for explaining the relationship between clock and data bits.

    The customer seems to be also satisfied with the answer, so I would like declare this case closed for now.

    Thank you for your help.

    Best Regards,

    Ryotaro Fukui

  • Hello,

    Can I ask two additional questions about the PCM4202 and PCM1804 I asked earlier?

    (4) Change digital filter settings

    Looking at the filter characteristics, it seems that the PCM4202 and PCM1804 both have a digital filter setting that limits the bandwidth to 48 kHz or lower when FS=96 kHz.

    Is it possible to set a digital filter that limits the bandwidth to 24 kHz or less when FS=96 kHz, which is the same bandwidth as when FS=48 kHz? If possible, the customer would also like to know how to change the settings.

    *Related descriptions (PCM1804 datasheet p13-14 Figure 17, 21) (PCM4202 datasheet P7-8)

    (5) How to reduce signal processing delays

    For both PCM4202 and PCM1804, is there a way to reduce the amount of delay in signal processing between input and output when FS=48kHz?

    Best Regards,

    Ryotaro Fukui

  • Hi Ryotaro,

    Could you make new post with these questions as we try to avoid run-on threads with indirectly related issues to initial issue. Meanwhile I will still review your questions.

    Best Regards,

    Carson

  • Hi Carson,

    I understand. Sorry for putting all questions together.

    I made a separate thread for the additional questions for PCM4202s, so I hope you can give me some advice there.

    Best Regards,

    Ryotaro Fukui