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AIC111: AIC111 connection to MSP430

Part Number: AIC111
Other Parts Discussed in Thread: MSP430FR5994,

Hi!

I'm trying to make this work with MSP430FR5994 but I'm not sure about what I built so far. Here's the circuit - .PDF file (updated).

I'd really appreciate some professional help on evaluating this schematic. I'm not sure BUF_DVDD and its shut down function (among other things).

Also, I'd like to make it a BoosterPack board from it, which will be the next step.

Thank you!

  • Hello Alex,

    I will take a look at this and reply by week's end.

  • Minor update to the schematic - added bypass cap for VSUB.

  • Thanks for update I will review soon and get back to you tomorrow

  • Hello Alex, This all looks okay. The point of buf_VDD is it should be set to voltage corresponding to digital voltage levels used in rest of system since regular VDD has max of 1.8V and the rest of system might be using 3.3V so buf_VDD would then be set to 3.3V. if buf_VDD is 0 then device cant communicate digitally.

    Anything else involving power supplies just pay attention to the electrical characteristics of the data sheet and the min and max values involved.

    Best Regards,

    Carson

  • I read the datasheet again and I don't really understand what this "Power pin for interface digital I/O circuit" means. Can you please explain?

    Also, VSUB is 3V, what do you mean "VDD has max of 1.8V". I should've put this to schematic probably.

    Anyway, sorry to bother, but please explain this.

  • Hello,

    Main attribute of device is its micropower quality which requires low voltage operation within the device which is why VDD supply must be small as specified here:

     from p.7 of datasheet

    Since the circuit this chip would be used in would probably have digital voltages higher than the max of DVDD there is a buffer stage incorporated in device which requires its own power thus  "Power pin for interface digital I/O circuit" means BUF_VDD needs higher voltage at whatever the digital voltage level of the rest system is which usually is around 3.3V so that it has capability to level shift voltages down to be used in the main portion of codec that runs at lower voltage or be shifted up to be outputted to rest of system. 

    Of course there is no min requirement for BUF_VDD so if rest of system is at 1.8V just apply 1.8V supply to BUF_VDD, but there is max at 3.6V

  • Thank you. I'm still learning...

  • No worries feel free to ask more questions either here if it is related or in new thread, but I will close this thread for now.

    Thanks,

    Carson

  • Carson, thank you for your time!

    You quoted this table with "TEST CONDITION". I understand this as just some particular case, because if we look at "Absolute Maximum Ratings", it says:

    and then then next table has 2 notes:

    (1) DVDD, VDD_OSC, and AVDD should be within 50 mV, preferably connected together. AVSS1, 2, DVSS, and VSS_OSC should be
    within 50 mV, preferably connected together.
    (2) Maximum (0.9 V, DVDD -0.5 V) BUF_DVDD 3.6 V

    As per note (2), if I understand this right, the BUF_DVDD should be:

    BUF_DVDD >= VSUB - 0.5 V. In my case it means BUF_DVDD should be >= 3 V, is that correct? If so, then I definitely should change buck-boost settings and make VSUB < 2.5V, for example.

    Another point of confusion is this, p.25:

    "Note A: P2.5 enables the MSP430F12x to shut down the AIC111 when desired".

    How does this note relate to "Power pin for interface digital I/O circuits"? I mean since BUF_DVDD is connected to P2.5, should V_HIGH of the MSP430 be >= VSUB - 0.5 V (according to the first requirement)?

  • Hello Alex,

    I understand your confusion let me ask the systems team on this matter and get back to you in 24 - 48 hours.

    Thanks,

    Carson

  • To clear things up: 

    Your AVDD = VSUB needs to be in that range of first screenshot I sent in my first reply.

    BUF_VDD = V_HIGH of MSP430 with the MSP430 being the defining factor

    Sorry for delay