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TLV320ADC6140: Inaccuracy in ADC acquisition Timing

Rohan Kamra
Prodigy 20 points
Part Number: TLV320ADC6140


Hello All

We have been using TLV320ADC6140 configured for 2 analog channels communicating over standard I2S protocol with our controller. The ADC chip is set as Master for I2S bus and using an external oscillator of 12.288MHz to generate the required clocks. We wish to acquire data at 48K Samples/second  as well as for 44.1K Samples/second at 32bit resolution. Currently, we have been testing the 48KS/s rate and found that the total acquisition time for acquiring 48000 samples is greater than 1 second by up to 10%. 
We have ruled out any issue with the controller by using an I2S slave sensor (MEMS Mic) and acquiring at 48KS/s from it. We do not face this timing issue in that case.  

We have tried replacing the external oscillator in case of a malfunctioning component, but that did not help us as well . 

Please suggest how to solve this.

Following are the register configurations being used by us pertaining to this:

Register 0x13 - 0b10000001  // Enable Master Mode ,  Auto Clock Config ,  PLL enable ,  not Forced Gate , FSYNC multiples of = 48 ,  MCLK=12.288MHz 

Register 0x14 - 0b01000100  // FSYNC=48kHz  ,  BCLK RATIO = 64

Register 0x16 - 0b00001000  // disabled MCLK_RATIO_SEL  ,  RATIO(for FREQ_SEL) = 256

Register 0x21 - 0b10100000  // GPIO Enabled as MCLK input

  • 0
    TI__Mastermind 23030 points

    In Master mode the W CLK and BCLK are given externally. Are you measuring 48Khz for WCLK and 48K*64=3.072 Khz on BCLK?

  • 0 in reply to Sanjay Dixit
    TI__Mastermind 23030 points

     

    Typo

    n Master mode the W CLK and BCLK are given externally. Are you measuring 48Khz for WCLK and 48K*64=3.072 Mhz on BCLK?

  • 0 in reply to Sanjay Dixit
    Prodigy 20 points

    According to our understanding, when TLV320ADC is in Master mode, only an MCLK is needed externally. The ADC chip generates the WCLK and BCLK to share with the controller. Currently, we do not have any other reliable way of measuring this apart from the controller itself which we use to benchmark the communication. Indeed, it seems there is some issue with the generated CLK cycles from the ADC chip which we wish to rectify.

  • 0 in reply to Rohan Kamra
    TI__Mastermind 23030 points

    I am sorry, I was actually referring to the slave mode.

    What do you measure on WCLK and BCLK Output on an oscilloscope? If WCLK /BCLK s not 48kHZ/3.072Mh then there may be an issue with

    clock setup for which i will look at your registers.

  • 0 in reply to Sanjay Dixit
    Prodigy 20 points

    We do not have an oscilloscope at hand currently. Thus, we used elimination process to figure out that the BCLK and WCLK generated by the ADC chip should be having some issue. We ruled out having a faulty oscillator by replacing it with a new one. We ruled out any driver issues on the controller by operating it with a slave I2S sensor . Now, the only possible issue could be something with our register configuration on the TLV320 chip itself. It would be great if you can have a look at it.

  • 0
    Prodigy 20 points

    To give you can an idea, a 32KB packet acquired at 48Khz, which should theoretically take approximately 85ms is taking 94ms to reach the controller. 

  • 0 in reply to Rohan Kamra
    TI__Mastermind 23030 points

    Try 0x02 in Register 0x16. Others seem OK.

    Try to measure waveform frequency.

  • 0 in reply to Sanjay Dixit
    Prodigy 20 points

    This did not help us. When using Master mode, we are facing this issue. We tried using TLV320ADC as slave, and we did not face the same problem. If that gives any clue to what problem we might be facing in the Master mode.

  • 0 in reply to Rohan Kamra
    TI__Mastermind 23030 points

    Can you try this? Let me know if any difference happens.

    w 98 01 01
    # 1mS Delay
    # -----------------------------------------------------------------------------
    # Begin Device Memory
    # -----------------------------------------------------------------------------
    # Page 0 (0x00) Dump
    # Select Page 0
    w 98 00 00
    # Wake up and Enable AREG
    w 98 02 81
    w 98 05 01
    # ASU configuration
    w 98 07 40
    # ASI Channel configuration
    w 98 0c 00
    w 98 0d 00
    w 98 0e 00
    # ASI master mode
    w 98 13 c1
    w 98 14 44
    # PDM Configuration
    w 98 1f b0
    # Page 1 (0x01) Dump
    # Select Page 1
    w 98 00 01
    #VAD configurations
    w 98 1e 00
    w 98 1f 00