• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 643 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM1808: SCLK clock variation tolerance

Kazuki Kuramochi
Genius 11635 points

Part Number: PCM1808

Hello Expert,

I have questions for PCM1808.
This device's SCLK accept following frequency under master mode.

min typ MAX Unit
256fs 2.048 12.288 24.576 MHz
384fs 3.072 18.432 36.864 MHz
512fs 4.096 24.576 49.152 MHz

My understanding for this table, this just showed what fs can be used.
For example, 96kHz is highest sampling frequency under 512fs case.
This because, if it is actual min/Max, there isn't margin for upper and lower limit fs from the point of view of  frequency variation.

Therefore, I'd like to  know about frequency variation tolerance for SCLK.
Then would you tell me margin for expected SCLK frequency?

Also, I think device will be into Clock-halt power down when SCLK frequency variation exceed above tolerance.
Is this understanding correct?


Best regards,
Kazuki Kuramochi

  • 0
    TI__Mastermind 23030 points

    In master mode the SCK is fed to the chip and if 512Fs is chosen LRCK will give FSCK/512 =Fs

    and BCK gives F s*64.

    The chart above may give an insight. It gives the allowed range for BCLK that can be output in Master Mode.  Tbclk=Tfs/64

    For 150 ns   Fs=104166Hz

    For 2000ns  Fs= 7812 Hz

    For Selection of 512Fs this means    53.33Mhz   and 3.99 Mhz.

    If the frequency of the clock goes above and below these limits the outputs should stop.

    However I am not sure if they have discrete windows for Fs . For example 48k range may be from 47.5k To 48.5k. This shall need to be checked with design team.

  • 0 in reply to Sanjay Dixit
    TI__Genius 11635 points

    Hi Sanjay,

    Thank you for your swift reply.
    I have questions for your answer.

    First, would you tell me why we can use BCLK's tolerance for SCK?
    Do you think BCLK's source is SCLK so you regard that we can use BCLK parameter for SCLK?

    Second, why you don't use LRCK for this calculation?
    If above my understanding is correct, LRCK should be used for this calculation as well but you chose BCLK.
    Moreover, SCLK has different tolerance when I use LRCK.(Also, I think ns for LRCK period's unit should be us. It is probably typo of datasheet)

    Also, I'm waiting update for whether there is individual tolerance for SCLK as like as 12.288MHz+-1%.

    Best regards,
    Kazuki Kuramochi 

  • 0 in reply to Kazuki Kuramochi
    TI__Mastermind 23030 points

    You are absolutely correct Kazuki -san,

    BCLK s derived from SCLK and since i saw the deviation of this one on the datasheet i inferred that this is fine to estimate the deviation of SCLK.

    LRCK could also be used but as you mentioned there seems to be some kind of typo in the datasheet.

    i will check about this error and the doubt about individual tollerance.

    Best Regards

  • 0 in reply to Sanjay Dixit
    TI__Genius 11635 points

    Hello Sanjay-san,

    Sorry for rushing you but is there any update regarding LRCK and individual tolerance?
    I'm waiting your update.


    Best regards,
    Kazuki Kuramochi 

  • +1 in reply to Kazuki Kuramochi
    TI__Mastermind 23030 points

    Answer sent over e mail