Hi,
I'm currently trying to configure the mentioned ADC to sample and incoming differential audio signal and transmit the data via I2S. My audio source is connected to input pins IN1L(P) and IN1R(M). The required sampling frequency is 16kHz. The audio master clock (AM) s generated using the BCLK of the I2S bus. Based on the constrains of the I2S bus, I set the BCLK frequency to:
BCLK = 16 (Bit width) * 2 (Channel) * 16kHz (sampling freq. WSCLK) = 512kHz.
Since I'll be using processing block 1, with AOSR = 128, I set MADC to 2, such that MADC * AOSR > IADC. NADC is set to 1. Therefore, a ADC_CLKIN frequency of at leat 4096 kHz is required. This clock is created using the PLL. For this, I set BCLK as the input clock to the PLL and configure K, R,P as follows:
K = J.D = 1.0, R = 8, P = 1.
Which means that fs = (PLLCLK_IN * K * R)/(NADC * MADC* AOSR * P) = (512kHz * 1.0 * 8)/(1 * 2 * 128 * 1) = 16kHz. I'm using the example configuration given in the datasheet as baseline. My configuration set is (first param is i2c reg, second is config value in hex):
00 00 // select page 0
01 01 // software reset
04 07 // setup clk mux
05 18 // P = 1, R = 8
06 01 // J = 1
07 00 // D(MSB) = 0
08 00 // D(LSB) = 0
05 98 // power up PLL, P = 1, R = 8
12 81 // power up NADC, NADC = 1
13 82 // power up MADC, MADC = 2
14 80 // AOSR = 128
1B 00 // use I2S with word length 16 bit, in slave mode
3D 01 // use processing block 1
00 01 // select page 1
3B 00 // unmute Left Analog PG, gain = 0db
3C 00 // unmute Right Analog PG, gain = 0db
36 0F // left adc input = diff pair IN1L(P) as PLUS and IN1R(M) as MINUS , with 0-dB setting
39 0F // right adc input = diff pair IN1L(P) as PLUS and IN1R(M) as MINUS , with 0-dB setting
00 00 // select page 0
51 C2 // power up left and right adc
52 00 // unmute digital volume control, gain = 0 dB
The configuration is successfully transmitted via I2C. When initiating an I2S transmission, i.e., my master device issues BCLK and WCLK, I'm assuming that the ADC begins to transmit the sampled data for each channel on the SDATA lane. To test this setup I'm using a function generator connected to the IN1L(P) and IN1R(M) pin, which generates an sinus signal at 20 kHz with an fitting amplitude. However, when initiating an transmission, the received data is a constant value. Therefore I'd like to ask whether my given configuration set is sufficient for my intended use case.
FYI: I also tried to configure IN1L(P) and IN1R(M) as single-ended channel, which also didn't work.
Thanks in advance.
