Other Parts Discussed in Thread: TLV320AIC3204,
Hi,
My question is about the maximum expected rise time and fall time. The Datasheet specifies (table 5.10) the maximum rise time and fall time, in slave mode, as 4nS; my system uses the component as an I2S slave mode with a 1.54MHz BCLK.
I found a note at a similar part (TLV320AIC3204, table 7.13, note 1), which indicates rise time and fall time for a lower clock rate than 10MHz (50nS for clock high and low) a maximum rise time and the fall time is 10nS.
Can I assume for the component TLV320AIC3120, the same note is applied for BCLK 1.54MHz?
quote: "(1) The BCLK maximum rise and fall time can be as high as 10 ns, if the BCLK high and low period are greater than 50 ns."
Regards,
Tal
