Part Number: PCM1808
Dear expert,
Customer wants to know how action will be when CLK was changed.
I want to ask about for 7.4.2 Clock-Halt Power-Down and Reset Function on page 18.
1. Was it for both master and slave mode?
The customer wants to in master mode.
2. For the last paragraph,
"To avoid ADC performance degradation, assertion of the clock-halt reset is necessary when changing system
clock SCKI or the audio interface clocks BCK and LRCK (sampling rate fS) on the fly."
What is the meaning of assertion of the clock-halt reset?
When was assertion of the clock-halt reset done?
There are the candidate for answer.
A. When the error
B. Just soon when change frequency such as 44.1k to 48k
C. After min of T(CKR)
I think this should be done after min of T(CKR) for each SCLK.
i.e.4us for 2MHz(256fs, 8kHz), 100us for 50MHz (512fs, 96k) .
And if is stared before than min of T(CKR) for each SCLK, it is not treated as 'Reset'.
Is this idea correct?
3. Does hung-up or some other issues will be occur if CLK is halt or changed when it is done within T(CKR)?
Customer think this should not be occurred because IC detect the error and reset, → MCLK confirmed or set → Fade in start process.
Is this idea correct?
Best regards,
Koki Tsushima
