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PCM5101A: Click Noise Due to Clock Synchronization?

Hideki Hayashi1
Expert 7540 points
Part Number: PCM5101A

Hi Experts,

Our customer found there is click noise and is guessing a cause is from clock synchronization. The noise is sometimes periodically but sometimes not heard.

the datasheet describes as below in 9.3.2.1

If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed.

Customer's clocks is that LRCK and BCK is synchronized, but LRCK and SCK is not.

I want to check if my understanding is correct or not that "more than +/-5 SCK change" means the rising edge of LRCK differs from SCK more than +/-5 SCK? 

Can you please explain in more detail? Also do you think clock synchronization leads click noise?

Best regards,

Hideki

  • 0
    TI__Mastermind 24330 points

    Hello Hideki, 

    the click noise is most probably the result of lack of synchronization of SCK and LRCK as it is needed for smooth operation. The part  requires the synchronization of LRCK and system clock, but does not need a specific phase. Please note that :

    "The serial audio interface typically has 4 connections SCK (system master clock), BCK (bit clock), LRCK (left
    right word clock) and DIN (data). The device has an internal PLL that is used to take either SCK or BCK and
    create the higher rate clocks required by the interpolating processor and the DAC clock. This allows the device to
    operate with or without an external SCK." 

    "The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at
    ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
    SCK from the BCK reference." 

    So If your customer can not sync LRCK to SCK ,  then simply ground SCK and it will then starts the internal sck and they should be fine.

    if you want to get more insight, take a look at the following link as it is an example of wrong choices of SCK or  Fs ratio

    https://e2e.ti.com/support/audio-group/audio-internal/f/audio---internal-forum/420835/pcm5100-pll-mode-fs-change-issue/1504481?tisearch=e2e-sitesearch&keymatch=pcm5100%20%20clk#1504481

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    TI__Mastermind 24330 points

    Has your customer check what I suggested in my last post ? ( GND the SCK and let the internal clks take over) this way we can see if the synchronization is an issue as we think?

    The part  requires the synchronization of LRCK and system clock. So for example Fs=48k and sck=256FS=12.288MHz, This means within a FS cycle, you have 256 fast clock (SCK) . So, as long as  it is not drifted by more that 5SCK in any direction (+/-) you should be okay. Now, according to datasheet " If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and BCK is completed." 

    Also you sent this plots , 

    Can you use a clean clk for SCK, seems an  echo or something on your clk..

    Regards,

    Arash