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TAS5717 datasheet inconsistency

Other Parts Discussed in Thread: TAS5717

Hi,

I'm looking at the datasheet for the TAS5717 from here:  http://www.ti.com/lit/gpn/tas5717

On page 33, the table shows the initialization value of System Control Register 1 (at 0x03) to be 0xA0.  On page 39, where the meaning of the bits in this register is described, it shows the initialization value to be 0x90.  If I read this register from the chip, i get 0xA0, so what is the meaning of the bits in that register?

 

One other thing... Am I correct in thinking that the minimal set of things I need to do to get sound to come out is:

  • Set the serial data format in SERIAL DATA INTERFACE REGISTER (0x04).
  • Clear bit 6 in SYSTEM CONTROL REGISTER 2 (0x05) to exit shutdown mode.
  • Set the master volume to something sensible.
  • Start sending audio data into the I2S port.

Are there any other steps to take?

Thanks

Nick

  • Hello Nick:

    Register 03 should read A0 - with bit D5 turned on.

    Here are the settings for getting this device running:

    • Set the serial data format in SERIAL DATA INTERFACE REGISTER (0x04).
    • Oscillator trim - geting the oscillator locked to Fs (0x1B 00)
    • Soft mute (0x06 FF) - minimize pop/click
    • Clear bit 6 in SYSTEM CONTROL REGISTER 2 (0x05) to exit shutdown mode.
    • Set the master volume to something sensible.
    • Soft unmute (0x06 00)
    • Start sending audio data into the I2S port.

    Best regards,

    Tuan

  • Hello Tuan,

    I'm using the TAS5717 audio amplifier controlled by an ARM-Cortex-M3 microcontroller on a custom board. I followed exactly your instruction list for getting the device runnunning. Further I proofed the communication on the I²C and I²S interfaces via oszilloscope, and measured a pwm-signal on the analog outputs of the amplifier (50% duty cycle). The problem is, that no audio signal consversion takes place. For test purposes I supply the IC with a simple continous ramp signal on both (l+r) channels. Error status register returns 0.

    I²S-configuration:

    I²S-32-fs-Format (Phillips) (fig. 28 datasheet), SCLK = 44100 * 2 * 16 Hz = 1411200 Hz, SCLK continues

    MCLK is absent (logical undefined). According to the datasheet the IC should be able to generate this main clock by itself?

    Do you have any idea solving this problem.

    Thanks in advance!

    Andreas