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PCM1863: Configuring 0x03 and 0x04 without output

Gust Zhang
Expert 5811 points
Part Number: PCM1863
Other Parts Discussed in Thread: PCM1864

Hi Team,

My customer occurs a abnormal phenomenon when using PCM1863. Customer uses VINL2 and VINR2 as input. The PCM1863 works in master mode and MCLK is 12.288MHz, BCLK is 6.144MHz, LRCLK is 96kHz. When customer configures 0x03 and 0x04 as 0xff, the read value shows 0x03 and 0x04 as 0x00(default mode). It means configuring 0x03 and 0x04 but have no output. What's more, configurating 0x20 as default mode(0x11) but shows 0x20 as 0x17. The more detailed log is as blow.

Best Regards,

Gust

  • 0
    TI__Mastermind 20845 points

    Hi Gust,

    Are all of the I2C transactions being ACK'D?

    Was the PCM1863 power cycled before these writes? the reason I ask is its odd for R0x20 to read 0x17 when you programed 0x11 and the reset value is 0x01 according to DS.

    I notice that you have Link PGA control enabled in P0R0x05, and Auto gain mapping enabled in P0R0x19. I would expect that the value in registers 0x02,3,4 would track 0x01 without being written. can you verify this?

    I have also seen cases on other parts where customers needed a few ms delay after switching register pages. can you ask the customer to try a small delay (~5ms) after switching pages?

    Regards,

    Arthur

  • 0 in reply to Arthur Brown
    TI__Expert 5811 points

    Hi Arthur,

    1.All of the I2C transactions are ACK'D, from customer's feedback, the I2C operation is normal.

    2.Yes, the PCM1863 is powered before writes, the writes is the power-on initialization.

    3.Without being written, 0x02,03,04 can track the 0x01. But in customer's application, they need set different value in left and right channel.

    4.For delay time, I have checked it with my customer. when in debugging, every time writing registers will delay 10ms.

    I have asked my customer dumped all registers value, you can refer it. Customer also try different value in 0x03 and 0x04, but the read value still is 0x00(reset and default value) .

    Fullscreen PCM1863 reg-dump.txt Download 
    testpcm
Console   : Get command :pcm1863 write read test
Console   : PCM1863 Start Init
Console   : reg config : reg=0x00, w=0x00,
Console   : reg config : reg=0x26, w=0x01,
Console   : reg config : reg=0x27, w=0x3f,
Console   : reg config : reg=0x05, w=0x67,
Console   : reg read : reg=0x26, dat=0x01,
Console   : reg read : reg=0x27, dat=0x3f,
Console   : reg read : reg=0x05, dat=0x67,
Console   : reg config : reg=0x06, w=0x42,
Console   : reg config : reg=0x07, w=0x42,
Console   : reg config : reg=0x08, w=0x42,
Console   : reg config : reg=0x09, w=0x42,
Console   : reg read : reg=0x06, dat=0x42,
Console   : reg read : reg=0x07, dat=0x42,
Console   : reg read : reg=0x08, dat=0x42,
Console   : reg read : reg=0x09, dat=0x42,
Console   : reg config : reg=0x0b, w=0x04,
Console   : reg config : reg=0x19, w=0x00,
Console   : reg config : reg=0x20, w=0x11,
Console   : reg config : reg=0x70, w=0x70,
Console   : reg read : reg=0x0b, dat=0x04,
Console   : reg read : reg=0x19, dat=0x00,
Console   : reg read : reg=0x20, dat=0x17,
Console   : reg read : reg=0x70, dat=0x70,
Console   : reg config : reg=0x00, w=0x00,
Console   : reg config : reg=0x01, w=0xfe,
Console   : reg config : reg=0x02, w=0xfe,
Console   : reg config : reg=0x03, w=0xfe,
Console   : reg config : reg=0x04, w=0xfe,
Console   : reg read : reg=0x01, dat=0xfe,
Console   : reg read : reg=0x02, dat=0xfe,
Console   : reg read : reg=0x03, dat=0x00,
Console   : reg read : reg=0x04, dat=0x00,
Console   : error : 1
Console   : read all page 0 reg 
Console   : reg config : reg=0x00, w=0x00,
Console   : reg read : reg=0x00, dat=0x00,
Console   : reg read : reg=0x01, dat=0xfe,
Console   : reg read : reg=0x02, dat=0xfe,
Console   : reg read : reg=0x03, dat=0x00,
Console   : reg read : reg=0x04, dat=0x00,
Console   : reg read : reg=0x05, dat=0x67,
Console   : reg read : reg=0x06, dat=0x42,
Console   : reg read : reg=0x07, dat=0x42,
Console   : reg read : reg=0x08, dat=0x42,
Console   : reg read : reg=0x09, dat=0x42,
Console   : reg read : reg=0x0a, dat=0x00,
Console   : reg read : reg=0x0b, dat=0x04,
Console   : reg read : reg=0x0c, dat=0x00,
Console   : reg read : reg=0x0d, dat=0x00,
Console   : reg read : reg=0x0e, dat=0x00,
Console   : reg read : reg=0x0f, dat=0xfe,
Console   : reg read : reg=0x10, dat=0x01,
Console   : reg read : reg=0x11, dat=0x20,
Console   : reg read : reg=0x12, dat=0x00,
Console   : reg read : reg=0x13, dat=0x00,
Console   : reg read : reg=0x14, dat=0x00,
Console   : reg read : reg=0x15, dat=0x00,
Console   : reg read : reg=0x16, dat=0xfe,
Console   : reg read : reg=0x17, dat=0x00,
Console   : reg read : reg=0x18, dat=0x00,
Console   : reg read : reg=0x19, dat=0x00,
Console   : reg read : reg=0x1a, dat=0x00,
Console   : reg read : reg=0x1b, dat=0x00,
Console   : reg read : reg=0x1c, dat=0x00,
Console   : reg read : reg=0x1d, dat=0x00,
Console   : reg read : reg=0x1e, dat=0x00,
Console   : reg read : reg=0x1f, dat=0x00,
Console   : reg read : reg=0x20, dat=0x17,
Console   : reg read : reg=0x21, dat=0x03,
Console   : reg read : reg=0x22, dat=0x03,
Console   : reg read : reg=0x23, dat=0x01,
Console   : reg read : reg=0x24, dat=0x50,
Console   : reg read : reg=0x25, dat=0x07,
Console   : reg read : reg=0x26, dat=0x01,
Console   : reg read : reg=0x27, dat=0x3f,
Console   : reg read : reg=0x28, dat=0x11,
Console   : reg read : reg=0x29, dat=0x03,
Console   : reg read : reg=0x2a, dat=0x01,
Console   : reg read : reg=0x2b, dat=0x10,
Console   : reg read : reg=0x2c, dat=0x00,
Console   : reg read : reg=0x2d, dat=0x00,
Console   : reg read : reg=0x2e, dat=0x00,
Console   : reg read : reg=0x2f, dat=0x00,
Console   : reg read : reg=0x30, dat=0x00,
Console   : reg read : reg=0x31, dat=0x00,
Console   : reg read : reg=0x32, dat=0x00,
Console   : reg read : reg=0x33, dat=0x01,
Console   : reg read : reg=0x34, dat=0x00,
Console   : reg read : reg=0x36, dat=0x01,
Console   : reg read : reg=0x40, dat=0x80,
Console   : reg read : reg=0x41, dat=0x7f,
Console   : reg read : reg=0x42, dat=0x00,
Console   : reg read : reg=0x43, dat=0x80,
Console   : reg read : reg=0x44, dat=0x7f,
Console   : reg read : reg=0x45, dat=0x00,
Console   : reg read : reg=0x46, dat=0x80,
Console   : reg read : reg=0x47, dat=0x7f,
Console   : reg read : reg=0x48, dat=0x00,
Console   : reg read : reg=0x49, dat=0x80,
Console   : reg read : reg=0x4a, dat=0x7f,
Console   : reg read : reg=0x4b, dat=0x00,
Console   : reg read : reg=0x4c, dat=0x80,
Console   : reg read : reg=0x4d, dat=0x7f,
Console   : reg read : reg=0x4e, dat=0x00,
Console   : reg read : reg=0x4f, dat=0x80,
Console   : reg read : reg=0x50, dat=0x7f,
Console   : reg read : reg=0x51, dat=0x00,
Console   : reg read : reg=0x52, dat=0x80,
Console   : reg read : reg=0x53, dat=0x7f,
Console   : reg read : reg=0x54, dat=0x00,
Console   : reg read : reg=0x55, dat=0x80,
Console   : reg read : reg=0x56, dat=0x7f,
Console   : reg read : reg=0x57, dat=0x00,
Console   : reg read : reg=0x58, dat=0x00,
Console   : reg read : reg=0x59, dat=0x00,
Console   : reg read : reg=0x5a, dat=0x00,
Console   : reg read : reg=0x5b, dat=0x00,
Console   : reg read : reg=0x5c, dat=0x00,
Console   : reg read : reg=0x5d, dat=0x00,
Console   : reg read : reg=0x5e, dat=0x00,
Console   : reg read : reg=0x5f, dat=0x00,
Console   : reg read : reg=0x60, dat=0x01,
Console   : reg read : reg=0x61, dat=0x00,
Console   : reg read : reg=0x62, dat=0x10,
Console   : reg read : reg=0x70, dat=0x70,
Console   : reg read : reg=0x71, dat=0x10,
Console   : reg read : reg=0x72, dat=0x0f,
Console   : reg read : reg=0x73, dat=0x04,
Console   : reg read : reg=0x74, dat=0x31,
Console   : reg read : reg=0x75, dat=0x00,
Console   : reg read : reg=0x78, dat=0x07,
Console   : read all page 1 reg 
Console   : reg config : reg=0x00, w=0x01,
Console   : reg read : reg=0x00, dat=0x01,
Console   : reg read : reg=0x01, dat=0x00,
Console   : reg read : reg=0x02, dat=0x00,
Console   : reg read : reg=0x03, dat=0x00,
Console   : reg read : reg=0x04, dat=0x00,
Console   : reg read : reg=0x05, dat=0x00,
Console   : reg read : reg=0x06, dat=0x00,
Console   : reg read : reg=0x07, dat=0x00,
Console   : reg read : reg=0x08, dat=0x00,
Console   : reg read : reg=0x09, dat=0x00,
Console   : reg read : reg=0x0a, dat=0x00,
Console   : reg read : reg=0x0b, dat=0x00,
Console   : read all page 3 reg 
Console   : reg config : reg=0x00, w=0x03,
Console   : reg read : reg=0x12, dat=0x40,
Console   : reg read : reg=0x15, dat=0x01,
Console   : read all page 253 reg 
Console   : reg config : reg=0x00, w=0xfd,
Console   : reg read : reg=0x14, dat=0x00,
Console   : pcm1863 wr test finish

    Best Regards,

    Gust

  • 0 in reply to Gust Zhang
    TI__Mastermind 20845 points

    Hi Gust,

    I will need 2 days to set try and replicate this on an EVM. this is unusual behavior I will try and replicate it.

    Arthur

  • 0 in reply to Arthur Brown
    TI__Expert 5811 points

    Hi Arthur，

    Do you have any update about the reiteration?

    Best Regards,

    Gust

  • 0 in reply to Gust Zhang
    TI__Mastermind 20845 points

    Hi Gust,

    I apologize I have not been able to test it. I have had a few pressing items I am trying to complete this week

    I will try to reproduce the same register writes and report my procedure next week.

    Regards,

    Arthur

  • 0 in reply to Arthur Brown
    TI__Expert 5811 points

    Hi Arthur,

    Do you have finished the test?

    Regards,

    Gust

  • 0 in reply to Gust Zhang
    TI__Mastermind 20845 points

    Hi Gust,

    I was able to reproduce the same effect

    I have been testing this and i think it might be the case that since PCM1863 is a 2 channel device that registers 0x03, and 0x04 only apply to the 4 channel versions of PCM186x.

    since the customer only has only two channel inputs (VINR2 and VINL2) this should be OK. 

    I notice that the customer has configured registers 0x06,7,8,9 such that both VINR2 and VINL2 are routed to two places. VINL2 goes to  ADC1L and ADC2L , and VINR2 goes to ADC1R and ADC2R. however PCM1863 does not have CH2L or CH2R ADC as it is a 2 channel variant of this part.

    Further more I tested a PCM1864 (4 channel) device with the provided register settings and was able to program registers 0x03 and 0x04 with no issue.

    Regarding register 0x20. I saw the same issue when I program 0x11 I read the value of 0x17.

    I don't think this matters since if bit 1 is set then bits 2,3 are ignored.

    Regards,

    Arthur