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Hi,
Just to check this that the Ratio Feedback Register represents the Input Sample Rate in the Numerator, and the Output Sample Rate is in the denominator ?.
Such that an input sample rate of 48kHz and output sample rate of 96kHz will result in the Ratio Feedback Register being set to 0.5.
And for an input sample rate of 192kHz and output sample rate of 48kHz will result in the Ratio Feedback Register being set to 4.
Thanks and regards,
Richard.
Hi, Richard,
I am assuming you are referring to registers 32 and 33, "SRC Ratio Readback Register."
In that case, I read the data sheet the same as your interpretation.
-d2
Hi Don,
Yes - registers 32 and 33. Thanks for the reply and confirmation.
Regards,
Richard.
Hi Jonas,
I have not got to this part yet - but I purchased the AES3 documentation where the entire document set provides the sub channel details.
I believe page 72 Table 5 - DIR Channel Status Buffer - corresponds to the AES3-2-2009 channel status content description.
The text on page 71 detailing byte 0 (zero) in Table 5 page 72 corresponds to the AES3 channel status description. As such Byte 2 corresponds to the data word size.
I would expect Address 0x04, which is Channel 1, Byte 2 to detail the Data Word Size for Channel 1 - using bits 5, 4, 3, but the AES3 also used bits 2, 1, 0 to set the state - so for bits 5, 4, 3, you will have either bits 5, 4, 3 meaning 24 bits, or 20 bits depending on status of Bits 2, 1, 0.
I don't think i can go any further as the AES3 is copyrighted.
I think the TI people can confirm this is correct or not - so you do not have to purchase the AES3 documents needlessly.
Regards,
Richard.