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PCM1862: Clock Halt and Error Detect

Koki Tsushima
Intellectual 875 points
Part Number: PCM1862

Hello, expert,

I received question about Clock Halt and Error Detect for PCM1862.

When CLK was changed without CLK halt as follows, from 44.1kHz x to 48kHz, will it be regarded as CLK error?

SCLK 22.579MHz ⇒24.576MHz

BCLK 2.822MHz  ⇒3.072MHz

LRCK  44.1KHz  ⇒ 48 kHz

If so, should PCM1862 will automatically re-operate after CLK error detected as follows sequence, which is written in 9.3.9.7 Clock Halt and Error Detect?


1. Mute audio output immediately (without volume ramp down)
2. Wait until proper clock is supplied (known as Clock Waiting State)
3. Restart clock detection. The PLL and all clock dividers are reconfigured with the result of the detection.
4. Start fade-in

Best regards,

Koki Tsushima 

  • 0
    TI__Intellectual 875 points

    Hello expert,

    Is it possible to answer soon?

    Sorry for rush.

    Regards,

    Koki Tsushima

  • 0 in reply to Koki Tsushima
    TI__Genius 13610 points

    Hello Koki,

    Sorry for wait. 

    If you dont follow procedure outlined here:

    You will most likely get error and it would go through the process you referenced when it does detect error.

    Best,

    Carson

  • 0 in reply to Carson Allen
    TI__Intellectual 875 points

    Hi Carson-san,

    I reviewed your comment I understood as follows.

    When change State A to Stage B (actually State B to Stage A for customer scenario, but it is same),

    it is have to obey 9.3.9.8. 

    If not, it should be detected error and should obey the 9.3.9.7.

    Is this understanding correct?

    And you said that "You will most likely get error and it would go through the process you referenced when it does detect error."

    What is meaning "most likely"?

    Is this mean that there are possibilities to error for misunderstanding 44.1kHz and 48kHz because it is just diff for few % ?

    If so, is it just for worst scenario or always happened? 

    Best regards,

    Koki Tsushima

  • 0 in reply to Koki Tsushima
    TI__Genius 13610 points

    Hello Koki,

    Your understanding is correct.

    And I say most likely meaning yes it will but there is a slight chance it might not, just because I have not actually gone and attempted to do it myself and see the result, but datasheet implies it will error.

    Best Regards,

    Carson

  • 0 in reply to Carson Allen
    TI__Intellectual 875 points

    Hello Carson-san,

    Thank you for your kind.

    I understood perfectly.

    I want to ask you for the worst case which cannot be detected changing the frequency

    Case 1.

    Is the noise continued to be output?

    If so. could you tell me how long does it continue for noise?

    Case 2.

    Can't PCM1862 sampling well because it is recognized as not changing the freq?

    If so,  how long does it continue? Will it be continued eternity? 

     

    And is it possible to predict that which stage (44.1kHz or 48kHz) is working on?

    My customer guessed that this was known by refer to register 115.

    But I think both frequency are for 011 therefore, it may be difficult to figure out.

    Do you have other ideas for figuring out?

    My customer guessed that PLL manual may be possible to know that.

    I am so sorry to rush you, but customer needs answer soon.

    Best

    Koki Tsushima

  • 0 in reply to Koki Tsushima
    TI__Mastermind 23030 points

    I can only make a guess about this. The actual situation shall have to be tried in a Board and this may be dependent on audio source behavior.

    I am assuming that customer is operating in slave mode and SCLK,BCLK AND LRCLK are provided to the chip from an external source.

    To my understanding a clock error is detected if:

    1. some Input signals are missing . (Table 15)

    2. The frequency or relationship of LRCK/BCK deviates (Table 16).

    Generally a switch over from 44.1Khz to 48Khz timing from the source does not happen instantly. It may be that during the switchover some signal disappears for a few cycles or the frequencies of the signal deviate for a short time as they go from one frequency to another

    If the deviations are such that the conditions outlined in table 15 or 16 are met then a Clock error may be detected. If detected the sequence described by customer would happen

    This may vary with the source generating the audio timing. The customer should look at the behavior of SCLK,BCLK,LRCK on a CRO when a timing switch from 44.1KHZ to 48K is attempted.

  • 0 in reply to Sanjay Dixit
    TI__Intellectual 875 points

    Hi Sanjay -san,

    Thank you for reply.

    My customer confirmed that switch over was done well for some audio source by measuring SCLK,BCLK,LRCK in "Slave mode".

    But he afraid for the worst case which cannot be detected switch over.

    So I want to update my questions as follows.

    Q.1. How many seconds does it take for returning when the IC cannot detected for the worst scenario?

    Q.2. How IC will be before the return?

    For those answers are this.

    A.1 & A.2

    " It may be that during the switchover some signal disappears for a few cycles or the frequencies of the signal deviate for a short time as they go from one frequency to another. If the deviations are such that the conditions outlined in table 15 or 16 are met then a Clock error may be detected. If detected the sequence described by customer would happen".

    For A.1

    I. Does "some signal disappears" mean that there are no noise and no audio output?,

      And which condition for this table?

     

    II. Or "frequencies of the signal deviate" means that cannot sync., but then how will it do like noise, or strange music etc ?

    III. Is it really possible to return without detection (or without table 15 and 16)? Was it miss-understanding for frequency forever?

    For A.2

    I. What is the meaning of a "few cycles"? Is it for LRCK? Can you calculate to time? 

    II. Is it possible to say the safety time for "short time"?

    Q.3. My customer confirmed that switch over was done well for some audio source by measuring SCLK,BCLK,LRCK in "Slave mode".

           But off course they cannot measure for all audio signal. 

           Customer wants to know which frequency ( 44.1kHz or 48kHz ) was used.

           Do you know some register which can be known frequency?

          I personally think that we can know by refer to register 115.

        But I also think both frequency are for 011 therefore, it may be difficult to figure out.

       

    Best regards,

    Koki Tsushima 

  • +1 in reply to Koki Tsushima
    TI__Mastermind 23030 points

    Response sent over e mail

  • 0 in reply to Sanjay Dixit
    TI__Intellectual 875 points

    I will be closed on E2E, but please help me again by e-mail.