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PCM4201: PCM4201 Mode and System Clock

Part Number: PCM4201


  1. What's the difference between master mode and slave mode of PCM4201; what applications are they used for, in my case, I want to realize sound source localization via microphone arrays, and I will use FPGA as controller.(By the way, is it possible to interface this ADC with FPGA?)
  2. The system clock is used to provide sampling frequency reference and it goes to audio DSP and ADC. But in master mode,  the PCM4201 generates the FSYNC and BCK clocks to communication, then I would liek to ask what's the usage of this system clock for audio DSP?
  • shall respond tomorrow

  • In Mater mode the device Generates the BCLK and LRCK . The Bit clock indicates presense of a new Data bit on the Digital output. These timings are made synchronous to a Master Clock that must be fed to the PCM 4201 DEVICE. This has to be a multiple of the  Sampling rate.

    If we like the device to make 44.1Khz sampling rate we need a SCLKI of 512*Fs=22.5Mhz. This timing can be generated in a DSP/FPGA.

    This SCKI  s synchronous to the  BCLK waveform generated and can be used as a reference to latch data if BCLK has jitter .

    You can connect in  master mode to an FPGA. Implement a serial to Parallel Data conversion in FPFA using SCKI and BCK as a Clock. 

  • 1.Dear Sanjay, if I understand correctly, you mean in master mode, SCKI can be provided by FPGA, right? But I wonder whether SCKI clock generated by FPGA will have jitter more easily?

    2.In master mode, can we use external oscillator (22.5MHz) as for, without connect oscillator to FPGA?

  • Yes you can use an oscillator to provide a clock to the PCM device