PCMD3180: Unexpected Latency on PDM Inputs 7 and 8

Shall look at this tomorrow

It looks to me that MIC7 and MIC 8  outputs are phase shifted by 90 deg from the Rest:

Does this phase shift reduce with tone frequency? for example if you make 100 hz does the shift change?

Also, have you tried connecting MIC7 AND MIC 8 to to MIC1 and MIC2 . Does the shift go away when this is done?

I have measured at different frequencies. The delay of PDM mic 8 compared to PDM mic 1 is slightly higher on 100Hz, but not a 90deg phase delay any more. Also, on higher tones, the shift does not follow frequency. The phase delay observed at different tones [samples, f_s=16kHz]:
100Hz: 10
200Hz: 8
300Hz: 7
400Hz: 7
500Hz: 6
600Hz: 7
700Hz: 6
800Hz: 6
900Hz: 7
1000Hz: 6
1500Hz: 6
2000Hz: 7

Physically we cannot swap the microphones, but we have tried it on multiple boards, and it is the same.
I have tried to swap PDM mic-->I2S slot allocation:
Originally, PDM1->I2S_left_0 and PDM8->I2S_right_4. And the signal received in I2S_right_4 was late.
When I swap config to: PDM1->I2S_right_4 and PDM8->I2S_left_0, then the signal in I2S_left_0 is late.

looking at issue. Shall reply tomorrow

What clock timings are you giving to the chip?

also, it it possible to connect the data of MIC7 to MIC1 keeping MIC1 OUTPUT DISCONNECTED?

We use 16kHz FCLK, and 4 x 16bit slots on the left and right sides too. So BCLK = 16e3*8*16 = 2.048 MHz. PDMCLK_DIV is set so that PDM clocks are 768_KHZ.

We have also tried disconnecting MIC1 and MIC7 microphone outputs, and routing MIC7 output to the PCM3180 input where MIC1 was connected before (PDMDIN1_GPI1). Repeated the 500Hz measurement without any SW modification. The MIC1 microphone reading in the SW (so actual signal of MIC7) is not phase shifted.

We use 16kHz FCLK, and 4 x 16bit slots on the left and right sides too. So BCLK = 16e3*8*16 = 2.048 MHz. PDMCLK_DIV is set so that PDM clocks are 768_KHZ.

We have also tried disconnecting MIC1 and MIC7 microphone outputs, and routing MIC7 output to the PCM3180 input where MIC1 was connected before (PDMDIN1_GPI1). Repeated the 500Hz measurement without any SW modification. The MIC1 microphone reading in the SW (so actual signal of MIC7) is not phase shifted.

We use 16kHz FCLK, and 4 x 16bit slots on the left and right sides too. So BCLK = 16e3*8*16 = 2.048 MHz. PDMCLK_DIV is set so that PDM clocks are 768_KHZ.

We have also tried disconnecting MIC1 and MIC7 microphone outputs, and routing MIC7 output to the PCM3180 input where MIC1 was connected before (PDMDIN1_GPI1). Repeated the 500Hz measurement without any SW modification. The MIC1 microphone reading in the SW (so actual signal of MIC7) is not phase shifted.

So that seems to confirm that the mic itself is not giving a phase shifted output.  Did you use the Clock for the Mic 1?

Yes, we used the clock of Mic1, as we have not changed the routes of the clocks.

Hello, is there any further idea to try? Do you experience the same on your side?

I shall send you some settings to try in a few hours

Have you tried phase calibration? For example for Channel 8 you could modify register 0x63 on page 0

I have tried setting 100 and 255 values to register 0x63. Delay is added as expected: with this, channel latency is adjusted [0..255]/6.144MHz, so adjustable max latency is 41.5 usec configurable in 162ns steps. With f_s=16kHz, we have sample time T=62 usec. The delay added with phase calibration is therefore below a single sample time. But I can clearly see that channel 8 is delayed as around as expected if I set values 100 and 255 to register 0x63.

What else could be the cause of the unexpected 6 samples delay?

Hi Roland,

Sanjay will be out of office for a few days, so I will reply. Are you using PPC3 to configure the register settings? It is by far the easiest way to get a good configuration for the device. If you do not have access I can grant it to you. 

https://www.ti.com/tool/PUREPATHCONSOLE

Brian

Select page 0
{ 0x00, 0x00 },
// Wake up and enable AREG
{ 0x02, 0x81 }, --
// ASI Configuration
{ 0x07, 0x40 }, --
//ASI Master mode Configuration
{ 0x13, 0x42 },
//PDM_CLK_DIV
{ 0x1f, 0xb2 },
//GPO1 Configuration
{ 0x22, 0x41 },
//GPO2 Configuration --
{ 0x23, 0x41 },
//GPO3 Configuration
{ 0x24, 0x41 }, --
//GPO4 Configuration
{ 0x25, 0x41 }, --
//PDMDIN1_GPI1/PDMDIN2_GPI2
{ 0x2b, 0x45 }, --
//PDMDIN3_GPI3/PDMDIN4_GPI4
{ 0x2c, 0x67 },--
//PDM Input Channel Enable
{ 0x73, 0xff },--
//ASI Output Channel Enable
{ 0x74, 0xff },

This assumes slave mode with BCLK of 2.046 Mhz, I2S 16 bit.,16khx

Can you see if this one helps.

Hello,

based on your proposal, I have made the following modifications:

 * Added write to register 0x00 value 0x00 (was same default 0x00 before)
 * Added write to register 0x13 value 0x42 (was default 0x02 before, so we disabled auto clock configuration)
 * Modified write register 0x1f value 0xb2 (was 0x42 before, chaning reserved bits)
 * Removed setting HPF setting register 0x6b value 0x03
 * Removed setting phase calibration register 0x63 value 0xff.
 * Kept the PDM input calibration registers 0x3c, 0x41, 0x46, 0x4b, 0x50, 0x55, 0x5a, 0x5f, as they are needed to operate on PDM inputs.
 * Kept the channel to I2S slot assignment registers 0x0f, 0x10, 0x11, 0x12, as they are needed to have the required channels in the I2S stream.

Eventually the config log looks:
[I] Exit hardware sleep mode
[I] Choose page 0
[D] I2C Write addr=0x00 data=0x00
[I] Exit software sleep mode
[D] I2C Write addr=0x02 data=0x81
[I] Set I2S output mode
[D] I2C Write addr=0x07 data=0x40
[I] ASI Master mode configuration
[D] I2C Write addr=0x13 data=0x42
[I] Configure input sources CH1..CH8 as PDM input
[D] I2C Write addr=0x3c data=0x40
[D] I2C Write addr=0x41 data=0x40
[D] I2C Write addr=0x46 data=0x40
[D] I2C Write addr=0x4b data=0x40
[D] I2C Write addr=0x50 data=0x40
[D] I2C Write addr=0x55 data=0x40
[D] I2C Write addr=0x5a data=0x40
[D] I2C Write addr=0x5f data=0x40
[I] Configure GPO1..4 as PDMCLK
[D] I2C Write addr=0x22 data=0x41
[D] I2C Write addr=0x23 data=0x41
[D] I2C Write addr=0x24 data=0x41
[D] I2C Write addr=0x25 data=0x41
[I] Configure GPI1..4 as PDMIN
[D] I2C Write addr=0x2b data=0x45
[D] I2C Write addr=0x2c data=0x67
[I] Enable PDM input channels
[D] I2C Write addr=0x73 data=0xff
[I] Configure CH5,6,7,8 to Right 1-2-3-4
[D] I2C Write addr=0x0f data=0x20
[D] I2C Write addr=0x10 data=0x21
[D] I2C Write addr=0x11 data=0x22
[D] I2C Write addr=0x12 data=0x23
[I] Enable I2S channel slots
[D] I2C Write addr=0x74 data=0xff
[I] Setting PDMCLK divider
[D] I2C Write addr=0x1f data=0xb2
[I] Power up PDM Channels
[D] I2C Write addr=0x75 data=0x60
[I] Autodetect FSYNC
[D] I2C Read addr=0x15 data=0x16

Now I receive all zeros in the I2S stream.
If I re-enable automatic clock configuration with register 0x13 default value 0x02, I receive the audio data as before.
I don't think the issue originates from global clock configuration, because it affects only PDM microphone inputs 7 and 8.

shall reply tomorrow

As a guess, the Decimation filters can cause 6 sample delay . Lets try the below and see if it does something.

1. 0x6c     0x00        switch of Bi-quad

    0x6B     0x21        Ultra low latency filter

2. I see the below timing used for 8 Mic Input. Lets try timing close to this. PDM CLK=64*Fs For Fs=16k  PDMCLK=1.024 Mhz. Lets try 1.5Mhz

0x1F    0X41

We can also as a test try the timing in the table below. You can try these changes in your fresh EVM.