TLV320AIC3104: Register configuration problem

Hi Jiahui,

Our expert Peter is out of office today and will respond to you early next week.

Brian

Hi Brian,

We look forward to your reply, thank you so much!

Best Regards,

Jiahui

Hi，

Thanks for your support.

But I still have some questions.

I have modified most of my configuration according to the configuration in the table, and a small part has not been modified; At present, when talking through the mic on the board, the voice can be heard on the mobile phone. Mic > codec > modem > mobile phone. There should be no problem in this channel, and the sound quality is also OK;

However, the channel from mobile phone > modem > codec > SPK is still not working. What SPK hears is noise, and the DIN and DOUT of codec have waveforms. Can you check again, and what else is wrong with the configuration of registers;

My current configuration is transmitted to the attachment;

root@udx710-module:/sys/bus/i2c/devices/3-0018#
root@udx710-module:/sys/bus/i2c/devices/3-0018#
root@udx710-module:/sys/bus/i2c/devices/3-0018# cat value
0, 00
1, 00
2, 44
3, a2
4, 1c
5, 57
6, 80
7, 0a
8, d0
9, 07
10, 00
11, 01
12, 00
13, 00
14, 00
15, 50
16, 50
17, ff
18, ff
19, 04
20, 78
21, 78
22, 78
23, 78
24, 00
25, 80
26, 00
27, fe
28, 00
29, 00
30, fe
31, 00
32, 00
33, 00
34, 00
35, 00
36, 00
37, c0
38, 00
39, 00
40, 00
41, 51
42, 00
43, 50
44, 50
45, 00
46, 00
47, 00
48, 00
49, 00
50, 00
51, 04
52, 00
53, 00
54, 00
55, 00
56, 00
57, 00
58, 04
59, 00
60, 00
61, 00
62, 00
63, 00
64, 00
65, 04
66, 00
67, 00
68, 00
69, 00
70, 00
71, 00
72, 04
73, 00
74, 00
75, 00
76, 00
77, 00
78, 00
79, 00
80, 00
81, 00
82, 00
83, 00
84, 00
85, 00
86, 00
87, 00
88, 00
89, 00
90, 00
91, 00
92, 00
93, 09
94, 00
95, 00
96, 00
97, 00
98, 00
99, 00

root@udx710-module:/sys/bus/i2c/devices/3-0018#

Please check the configuration again，thank you very much

Best Regards,

Jiahui

Hi,

So your ADC path (MIC1P/M) is working, but the DAC path to LINE output is noisy - is my understanding correct?

Your settings are not following what I have provided especially the PLL and its divider.

Please use the settings I have provided, if you decide to change then please use the PLL clock calculator from the product folder so the PLL criteria are met.

https://www.ti.com/product/TLV320AIC3104

See attached excel of your new settings.

4722.AIC3104.xlsx

Hi expert，

Thanks for your support.

But customer still have some questions.

"I tried to configure the register as provided by experts. At present, I can still hear a little sound at the SPK end, but there is a lot of noise, which is similar to the feeling of great bottom noise plus echo.

In addition, I see that the circuit diagram expert posted on his post is also output to left-lop, while the circuit design on my side is only connected with right lop and right LOM. Please see the schematic diagram I posted back to the expert to see if there are better suggestions."

Thank you

Hi,

Try this configuration as I streamlined further the settings as shown below.

If the issue persists, please provide the scope capture of the wclk, bclk and the registers read back from your system.

5148.AIC3104.xlsx

hello

hello 

The question was raised by me, I used the configuration you recommended, but there was still a great noise, and a little human voice could be heard in the noise, I read the register configuration during my call, in reg0303.txt,  and recorded the voice  for 12345678910.m4a;

root@udx710-module:/sys/bus/i2c/devices/3-0018#
root@udx710-module:/sys/bus/i2c/devices/3-0018# cat value
0, 00
1, 00
2, 44
3, a2
4, 1c
5, 57
6, 80
7, 0a
8, d0
9, 07
10, 00
11, 01
12, 00
13, 00
14, 00
15, 50
16, 50
17, ff
18, ff
19, 04
20, 78
21, 78
22, 78
23, 78
24, 00
25, 80
26, 00
27, fe
28, 00
29, 00
30, fe
31, 00
32, 00
33, 00
34, 00
35, 00
36, 00
37, c0
38, 00
39, 00
40, 00
41, 51
42, 00
43, 50
44, 50
45, 00
46, 00
47, 00
48, 00
49, 00
50, 00
51, 04
52, 00
53, 00
54, 00
55, 00
56, 00
57, 00
58, 04
59, 00
60, 00
61, 00
62, 00
63, 00
64, 00
65, 04
66, 00
67, 00
68, 00
69, 00
70, 00
71, 00
72, 04
73, 00
74, 00
75, 00
76, 00
77, 00
78, 00
79, 00
80, 00
81, 00
82, 00
83, 00
84, 00
85, 00
86, 00
87, 00
88, 00
89, 00
90, 00
91, 00
92, 00
93, 09
94, 00
95, 00
96, 00
97, 00
98, 00
99, 00
100, 00
101, 00
102, 02

root@udx710-module:/sys/bus/i2c/devices/3-0018# test_modem_send_ap_alreadyinit_once ret 1 [11]
test_modem_send_ap_alreadyinit_once ret 1 [12]

my bclk is about 512kHz, and wclk is about 16kHz,as shown in the picture

Is the path we are choosing unfiltered? I'm making a lot of noise. Should I configure the page1 register for filtering? Can you give me the recommended configuration

Hi,

From your settings above you are not using my recommended settings as pointed out above.

See attached sheet and make sure your registers are what were written in either column D or E and looking at your clocks above the levels are not the same for BCLK and WCLK.

0753.AIC3104.xlsx

Do you recommend this column of data “TI Suggested setting for 16KHz” ？

I seem to have made a mistake and configured according to this column “New data” of data. I will verify the configuration according to this column “TI Suggested setting for 16KHz” and feedback the result as soon as possible，thanks

hello，I reconfigured the registers for testing, but the noise still exists, which seems to be more noisy than before. I recorded the voice when I made a phone call and uploaded the register configuration when I made a phone call, please help to check.

I think the value of D in PLL is 5618, 01 0101 1111 0010, a 14-bit unsigned integer, which is made up of the top 8 bits in reg5 and the top 6 bits in reg6. The lower two digits in reg6 are reserved 0, so reg5 should be 0x57, reg6 should be 0xC8, Is that right?

and the levels of BCLK and WCLK，BCLK and WCLK is codec output，What happens if their levels are different？

0304along's data.AIC3104.xlsx0304.m4a

Hi,

For D value, that's correct you will enter 0x57C8 because of the formatting. Are these registers read back from your system through i2cdump?

There're VIL and VIH requirements for I2S and normally these I2S signals are of the same level but yours are different so I'm wondering why are they different and what's your VDDIO level?

Now we need to debug further, can you just analyze the ADC by itself and make sure you get the correct signal? What that means is you analyze the digital that goes to the host and see if you have the signal you sent from your MIC1 input. If ADC side is correct then do the same for the DAC send something from your host through DAC to your Line Right output.

1. these registers read back from my system through i2c read

2.IOVDD level is1.8

3.Do you mean separate verification for recording and broadcasting? My current software may not support this validation，However, from the current status of the ADC, the voice in the MIC heard by the peer end is clear

Hi Along,

Just FYI that Peter was out of office for Monday and should be back tomorrow.

Brian

1. OK, that's good.
2. So do you know why WCLK level is not 1.8V like BCLK?
3. Yes, what do you mean by voice is clear at the peer end? Which path and output is this?

Since the registers read back is correct, the cause of the issue might come from the host side. That's the reason we need to isolate.

Do you have instrument like Audio Precision PSIA or are you able to send/capture the digital through other software?

hi Peter

I have solved the problem of noise，I set the reg10 that "Audio Serial Data Word Offset Control" is 1, the noise is gone;

At present, there is another problem that the volume of my DAC is too low. although I set reg44 to 0x0 and reg93 to 0x99, the volume is not high enough. Is there any way to raise the volume

It sounds like your host timing is not aligned, is it configured to I2S format? I suggest you analyze your digital side to and from host.

For volume those are the correct registers, you can set them accordingly. 

hi Peter

Is there any other register that can be used to turn up the volume? our customer reported that the volume is small, the same speaker is loud on other Codec

Hi,

For volume/gain these are the registers for your audio path:

• Left ADC in register 15 and right ADC in register 16
• MIC1L/LINE1L gain in register 24
• Right DAC gain in register 44
• Right LOP/M volume in register 93

Regards.

Ok, I see；Is the  volume of spk low because only connected to the RIGHT_LOP/RIGHT_LOM?  If he is connected to the high-power output driver, will the volume be higher?

the ADC have some echo，how I can echo cancellation

Can I change my path, Increase my gain？

hi 

Which block diagram do you mean？

Can you help me explain the register configuration that needs to be modified for "PGA_R path BYPassing the Digital" please

thanks

hi  peter

I increase the volume by adjusting the hardware, but the background noise also increases, how should I deal with it？

I did not use the bypass path，the path is the same as before, as shown in the figure, I just made some hardware changes. turned up the volume and background  noise, How to Reduce Noise?

I thought you mentioned you have solved the noise problem by adding an offset.

As mentioned before try with the bypass mode and see if it's good, my suspicion is of the host and you need to isolate if you intend to use this path.

This is tied to your comment of adding an offset fix the noise it tells me some timing issue in the host.

I did not use the  the bypass mode, I'm still using the old plan like the  picture. My problem is background  noise, It's not the same noise as last time.

The background noise is always been there, but the volume is small, so the noise volume is also small.

Now after adjusting the hardware and amplifying the volume, the background noise is also amplified, so I hope to find a way to reduce the background noise

How much power can be driven by the left/right output and HPROUT output in the absence of a power amplifier circuit at the CODEC output ?

Hi Jiahui,

Peter is out of office today and will return to answer your questions Monday.

Thank you for your patience,

Jeff

Hi,

Again on the noise, please check the ADC and DAC path separately as suggested to isolate the cause.

You can find the Power (Po) for HP in the datasheet section 8.5 and for line you can calculate that as well from the spec table according to the load connected.

Regards.