PCM4202: Origin of Tone produced inside the PCM4202

https://e2e.ti.com/support/audio-group/audio/f/audio-forum/773104/faq-pcm4220-pcm4220-idle-tone

Perhaps this reference helps

The reference to PCM4220  gives me hint that the PCM4202  might have the same basic characteristic/flaw.

I will experiment with the applied VCC level for the PCM4202 but it leaves me with an unhappy situation:  since no specific answer is given from T.I. , and the matter could be related to date codes insofar as presence of the 'tone' versus applied voltage, the combination of these factors it seems that I might never have a stable design.  

Question:

Considering temperature does influence the frequency and amplitude. Increased Temperature tends to have the tone shift toward a lover frequency and at certain temperatures the tone essentially disappears into the noise floor ( within a 3 or 4 degrees Celsius window) .  Then toss in a possible voltage factor, per the above referenced 'solution' and I ask:  how can this be made into a stable design?

Jaye

Hi Jaye,

Just FYI that Sanjay is out of office until Wednesday this week.

Brian

I would suggest to try at Vcc of 4.35v . You can then evaluate the effect of temperature.

Jaye,

Try inverting the polarity of the system clock.  The PCM4202 samples on the falling edge of the system clock, and system designs using a DSP or other clocked logic will have substantially less jitter (phase noise) on one clock edge than the other. Make sure to include series resistors (150R-330R) on the clock signals driving the PCM4202 (assuming it is in slave mode).

I saw a 10+ dB reduction in flat-band noise as well as complete elimination of idle tones by making these two changes in my design.  It is now slightly quieter than the datasheet spec.

As soon as I get my project off the ground I'm going to write a detailed forum post with my findings.  This information ought to be in the datasheet or an application note.

Jaye,

I have observed idle tone behavior in the EVM as well.  I can also make it go away by altering the clock polarity (when provided externally).  Are you using the onboard oscillator, an external clock on the BNC connector, or an external clock on the audio serial port header?

The shift in the noise floor when resetting the AES transmitter is related to the initialization of the PCM4202, which does not have a "clock halt" reset feature that I am aware of.  If the clocks are interrupted for any reason you need to initiate a hardware reset cycle on the PCM4202 using the reset pin.

Sigma-Delta sampling converters are extremely sensitive to clock phase noise.  Strongly correlated (e.g. at some precise regular interval) phase noise can cause idle tones when patterns in the modulator bitstream fall into the audio passband.  The sensitivity to temperature and voltage arises because these patterns are strongly influenced by DC offset in the modulator.  I can go into further detail if you are interested.

Parasitic coupling from adjacent traces on the board (such as the serial bit clock or left/right clock) will cause strongly correlated phase noise in the system clock.  Ideally there should be no other signals changing logic states during the system clock falling edge.  Unfortunately it is not uncommon for the various audio clock signals to be all aligned at the falling edge, as this is how they get generated when you divide them down with a binary counter.  This means that the system clock, bit clock, and left/right clock might be all transitioning from high to low at the same time in operation, causing a small shift in the precise timing of the falling edge of the system clock.

This information is poorly documented in the datasheet.  In fact, I haven't read any datasheet from any manufacturer that explicitly states which clock edge drives the sampling converters - surprising considering it makes such a big difference.

I wouldn't dismiss the PCM4202 just yet, please do give this a try.  Like I mentioned above, I was able to slightly exceed the datasheet spec on unweighted dynamic range with my design (with no idle tones!), even using noisier opamps in the low-pass filter stage driving the ADC inputs.

Jeff,

Running in Master mode leaves me thinking that the clock phasing cannot be changed.  My ADC is the system master to which all downstream processing is synchronized..

However you spurred a memory of a similar issue.  The earlier issued seemed unstable so I contacted the design engineer of the respective device and he provided interesting insight. Seems if the clock came within about 3mV of the rails it would charge pump the silicon and the logich thresholds would become ambiguous.  We placed a series resistor in the master clock line much as you mentioned but added a second resistor to ground, thereby forming a voltage divider to reduce the logic levels and make the High level <3mV below the upper rail.  In the end the performance was rock steady.  Just maybe something similar is going on inside the PCM4202..  At my end I have asked a second engineer to look at this as a possible problem fix.  In any event I do wish to understand the exact cause of the present issue.

Thank you.

Jaye

Hello Jaye,

Was your test done on an EVM? 

Sanjay,

Yes, the testing is done on your EVM.  The results fairly duplicated what is occurring within my product.

Jaye

Jaye,

Let me try to get hold of an EVM and take a look at this.

Hello Jaye,

We have ordered an evaluation board for this device. It should hopefully arrive within a week. I will then look at the Idle Tone Issue .

Best Regards

Hello Jaye,

would it be possible to let me know that timings you operated the chip on? 

Thank you..

Jeff -- all of the above is very interesting! I built a converter around the 4202 and noticed idle tones. oddly they appeared only with sample rates that were a multiple of 48 kHz, not 44.1 kHz. I run the chip in slave mode, with clocks provided by an Si5344D synthesizer. I never did get to the bottom of it.

Inverting the polarity of the modulator clock output from the Si5344D is a simple register change. Hopefully I can test this soon.

I believe the critical factor here is other clocked logic in the design should operate on the rising edge of the system clock, while the PCM4202 samples on the falling edge.  In particular, the I2S clock and data signals must not change states on the falling edge of the system clock.  This might require re-configuring the I2S master, or driving the PCM4202 from an alternate output of the Si5344D.  If you're using LVCMOS outputs then it looks like you can use the OUtxb pin.

Jeff,   In my system the down-stream logic adheres to the Positive transition of the bit clock occurring at the mid-time of the data bit.  It is well understood that the data transitions occur co-incident with negative transition of the bit clock.

The comment from Andy about the 44.1K performance is interesting.  I work with professional audio and seldom deal with 44.1K

In my testing I have examined the I2S data direct from the PCM4202, using the 'Prism' audio analyzer (  a feature my AP system does not have ). In the I2S data stream the tone is clearly present as mentioned at the beginning of this discussion.

In my mind it is clear that a design flaw exists inside the PCM4202.

Thank you.

Jaye

Jaye,

I agree on the timing of the serial data and left/right clock signals coinciding with the falling edge of the serial bit clock (as per the I2S specification).  I would like to draw attention to the timing relationship between the system/master clock and the serial bit clock.  If the bit clock is changing states on the falling edge of the system/master clock then there is potential for idle tones to be present.

I have likewise done all of my testing at 48kHz as the product I am working on is targeting a professional application, so I have performed very little testing at 44.1kHz.  If idle tones are not present when running at 44.1kHz, then the first thing I would ask is what the master clock ratio is, and if it is different from what was used at 48kHz.  Also of interest is if there is any notable difference in the noise floor at the two rates, as they are close enough that the performance should be very similar.

Unfortunately my budget doesn't allow for any Audio Precision test instruments (yet!), so all of my testing has used GNU Radio running some carefully prepared flowgraphs.  The product I am working on relies on Dante audio-over-IP, so my audio clocks originate from a Brooklyn II card.  With it set to output a master clock of 512fs (24.576MHz) the serial bit clock transitions on the falling edge of the master clock.  I have observed idle tones from the PCM4202 in this configuration, but inverting the polarity of the master clock eliminates them completely, in addition to a flat-band noise floor that is 1.6dB lower.