Hi,
I have downloaded linux driver for aic3262 from "/cfs-file/__key/communityserver-discussions-components-files/6/3262_2D00_E2E.zip" and integrated the same into my kernel.
I also have mkcfw tool to generate "tlv320aic3262_fw_v1.bin" which is requested by Linux driver.
Please check cfd file, Only PRB mode1 and PLL setting has been used, miniDSP programming is not there.
PFA cfd file and PLL setting
#------------------------------ # DAC/ADC CLOCK CONFIG #------------------------------ # MCLK is 38.4MHz # PLL_CLK = r*j.D/p = 1*5.1200/2 = 98.304 MHz # P=2, R=1 : XPPP RRRR sreg[PLL_PR_POW] = 0b.0100001; # J=5 :XXJJ JJJJ sreg[PLL_J] = 0b..000101; # D= 1200. MSB=04 LSB=B0 sreg[PLL_D_MSB] = 0x04; sreg[PLL_D_LSB] = 0xb0; # DIV = 1 XVVV VVVV (128,1-127) sreg[PLL_CKIN_DIV] = 0b.0000001; # NDAC = 2: XVVV VVVV (128,1-127) sreg[NDAC_DIV_POW] = 0b.0000010; # MDAC = 8 : XVVV VVVV (128,1-127) sreg[MDAC_DIV_POW] = 0b.0001000; # DOSR = 128 DOSRMSB = 0x00 DOSRLSB = 0x80 sreg[DOSR_MSB] = 0x00; sreg[DOSR_LSB] = 0x80; # NADC NADC = 2 sreg[NADC_DIV_POW] = 0b.0000010; # MADC MADC = 48 sreg[MADC_DIV_POW] = 0b.0001000; # AOSR = 128 sreg[AOSR] = 128; #------------------------------ # ASI1 CLOCKS #------------------------------ # ASI1 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01 sreg[ASI1_BCLK_N_CNTL] = 0b......01; # BCLK N DIVIDER = 4 : XVVV VVVV sreg[ASI1_BCLK_N] = 0b.0000100; # WCLK N DIVIDER = 32 : XVVV VVVV sreg[ASI1_WCLK_N] = 0b.0100000; # ASI1 BCLK WCLK OUTPUTS : XBBB XWWWW # BCLK = BCLK DIV OUT # WCLK = ASI1 WDIV sreg[ASI1_BWCLK_OUT_CNTL] = 0b.000.010; #------------------------------ # ASI2 CLOCKS #------------------------------ # ASI2 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01 sreg[ASI2_BCLK_N_CNTL] = 0b......01; # BCLK N DIVIDER = 4 : XVVV VVVV sreg[ASI2_BCLK_N] = 0b.0000100; # WCLK N DIVIDER = 32 : XVVV VVVV sreg[ASI2_WCLK_N] = 0b.0100000; # ASI2 BCLK WCLK OUTPUTS : XBBB XWWWW # BCLK = ASI2 BDIV # WCLK = DAC_FS sreg[ASI2_BWCLK_OUT_CNTL] = 0b.010.000; #------------------------------ # ASI3 CLOCKS #------------------------------ # ASI3 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01 sreg[ASI3_BCLK_N_CNTL] = 0b......01; # BCLK N DIVIDER = 4 : XVVV VVVV sreg[ASI3_BCLK_N] = 0b.0000100; # WCLK N DIVIDER = 32 : XVVV VVVV sreg[ASI3_WCLK_N] = 0b.0100000; # ASI3 BCLK WCLK OUTPUTS : XBBB XWWWW # BCLK = ASI3 BDIV # WCLK = DAC_FS sreg[ASI3_BWCLK_OUT_CNTL] = 0b.100.000;
1) Linux request firmware "tlv320aic3262_fw_v1.bin" and try to do PLL setting and PRB mode setting
can you please tell me do i need to set audio routing (HP for playback and IN2 for capture) from Linux userspace via amixer
or i need to add this details in Firmware file ?
2) If codec works as Master can i change PLL setting runtime via Linux driver ?
3) If only PRB modes has been used, ADC and DAC who will do ADC and DAC power up
do i need to do that from Linux userspace via amixer ?
