TAS2505-Q1: How to configure the registers regarding clock configuration?

Shawn_Wang

Part Number: TAS2505-Q1

Hi team

Could you help give the correct PLL configuration for this applicaiton?

Audio signal: 16bit,16k sample rate
MCLK: 2MHz
BCLK: 512k
PLL_CLKIN=MCLK=2MHz
CODEC_CLKIN=PLL_CLK

I found a recommendation in this post(Link) but it should not be suitable for 2MHz MCLK input based on the description in this application note: Link - 2.6.1 PLL part.

And could you help also check if the MCLK and BCLK is needed to be changed for this application?

Thank you.

over 3 years ago

0 Jeff McPherson over 3 years ago

TI__Mastermind 47255 points

Hi,

From what you've given, your MCLK and BCLK are fine and don't need to be scaled by the PLL. Your BCLK = 16k * 2 channels * 16 bits = 512kHz. Your MCLK = N * fs = 125 * 16k = 2MHz. You should be fine using the simple dividers for DAC clocks and not using the PLL. If you do want to use it, you can configure all factors to 1. Register 4 controls the multiplexing of the clocks and can be found in 5.1.1 in the Application Notes as well as the PLL factors.

I hope I answered your questions,

Jeff

0 Shawn_Wang over 3 years ago in reply to Jeff McPherson

TI__Expert 3811 points

Hi Jeff

Thanks for your prompt reply.

Jeff McPherson said:
If you do want to use it, you can configure all factors to 1.

In case there is some misunderstanding, could you help give a detailed recommendation like the following table? Thank you.

0 Shawn_Wang over 3 years ago in reply to Jeff McPherson

TI__Expert 3811 points

Hi Jeff

I have got their code and could you help check if there is something wrong?

The customer found the sound quality is bad and speaker input signal is abnormal.

// page 0
DacWriteReg(0x00,0x00);
DacWriteReg(0x01,0x01);
// page 1
DacWriteReg(0x00,0x01);
DacWriteReg(0x02,0x00);
// page 0
DacWriteReg(0x00,0x00);
DacWriteReg(0x04,0x03);
DacWriteReg(0x05,0x94);
DacWriteReg(0x06,0x0A);
DacWriteReg(0x07,0x00);
DacWriteReg(0x08,0x00);

sysdelayms(15);

DacWriteReg(0x0B,0x8A);
DacWriteReg(0x0C,0x84);
DacWriteReg(0x0D,0x00);
DacWriteReg(0x0E,0x80);
DacWriteReg(0x1B,0x00);
DacWriteReg(0x1C,0x00);
DacWriteReg(0x3C,0x02);
// page1
DacWriteReg(0x00,0x01);
DacWriteReg(0x01,0x10);
DacWriteReg(0x0A,0x00);
DacWriteReg(0x2E,0x00);
DacWriteReg(0x30,0x10);
DacWriteReg(0x2D,0x02);
// page0
DacWriteReg(0x00,0x00);
DacWriteReg(0x3F,0x90);
DacWriteReg(0x41,0x00);
DacWriteReg(0x40,0x04);

0 Jeff McPherson over 3 years ago in reply to Shawn_Wang

TI__Mastermind 47255 points

Hi Shawn,

I made a mistake understanding your question. While the PLL isn't necessary for I2S alone, I forgot to consider the DAC portion. Below I've attached a table like the one you asked for on possible PLL configurations. Notice that I have BLCK as PLL_CLKIN because using MCLK = 2MHz yielded no solution. Please adjust your code to this new configuration.

Thank you,

Jeff