PCM1808: performance degradation

Yasushi Fujiwara

Part Number: PCM1808

Hello Experts,

My customer has question. Regarding the section of "7.4.2 Clock-Halt Power-Down and Reset Function", datasheet mentioned that “To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) must synchronize with SCKI within 4480 / fs after the resumption of SCKI.”. What kind of performance of ADC will degrade if the above timing is violated?

Best Regards,
Fujiwara

over 3 years ago

0 Jeff McPherson over 3 years ago

TI__Mastermind 47195 points

Fujiwara-san,

I will check with our design team and see if there is any specific degradations that can occur and let you know what we find.

Best Regards,

Jeff

0 Jeff McPherson over 3 years ago in reply to Jeff McPherson

TI__Mastermind 47195 points

Fujiwara-san,

According to our design team, this is in reference to the clocks taking too long to frequency lock i.e. maintain an integer ratio between SCLK and LRCLK. This mismatch will not harm the device in anyway, but it will reduce the effectiveness of the device such as the conversion quality, THDN, and other metrics.

Best Regards,

Jeff

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PCM1808: performance degradation