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PCM1863: SCK output from GPIO in Slave mode

Mochi
Genius 3935 points
Part Number: PCM1863
Other Parts Discussed in Thread: TLV320ADC5140

Hello,

We plan to use PCM1863 in Slave mode with BCK reference input PLL mode to generate SCK. And output SCK from GPIO1 to external PCM-DAC SCK input.

In this case we will set following KEY registers for SCK clock tree. Is there any concern?

  Reg32 0x20 B5=BCK PLL mode, B4=Slave mode

  Reg40 0x28 B1=PLL input BCK, B0=PLL Enable

  Reg37 0x25 Set PLL divider value for SCK

  Reg16 0x10 B6-4=011, GPIO1 output internal SCK

 

One of our curiosity is Figure33 block diagram described "Master mode only" on tha datasheet. Is this true limitation of clock tree?  

 

Regards,

Mochizuki

  • 0
    TI__Mastermind 32160 points

    Hi Moschizuki-san,

    Make sure that when you write register 32 you assign the proper clock to each device as well. Otherwise I don't see any glaring issues.

    The "Master Mode Only" is in fact a limitation. In master mode the clock pins act as outputs like described. In slave mode the clock pins must act as inputs and so that section will be unavailable. 

    Thanks,

    Jeff

  • 0 in reply to Jeff McPherson
    Genius 3935 points

    Hello Jeff-san,

    I appreciate for your prompt and precise answer.

    We will work with our customer to proceed EE product development.

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    Genius 3935 points

    Hi Jeff-san,

    We are still struggling to get PLLed SCK output from GPIO1 pin.

    There are two test results, please find attached scripts.

     Test SCKO PLL.xlsx

    Test 1:

    PLL divider is "CLKDET auto setting".

    Such as Fs=44.1KHz, 64BCK, P=1, R=2, J=16, D=0, PLL out is 2048Fs=90.3168MHz.

    DSP1=1/4, DSP2=1/8, ADC=1/16 and SCK out=1/16=128fs=5.6448MHz is expected SCK from GPIO1 output.

    As 0x10 set to 0x35 for GPIO1 output internal SCK.

    But 0x14 read out 0x00 GPIO1 input status=0 , resulted in no clock output from GPIO1.

     

    Test 2:

    In this case, we connect SCK input together with BCK and LRCK, it is slave mode but no PLL.

    Then 0x14 read out 0x02 GPIO1 input status=1, SCK output is present on GPIO1.

     

    Could you review our scripts and suggest us how can we get SCK output from GPIO1 while PLL is enabled ?

      

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 32160 points

    Hi Mochizuki,

    I can look at this and try to find the problem. I will get back to early next week. For book-keeping purposes please wait to hear back from me before replying.

    Thanks,

    Jeff

  • 0 in reply to Jeff McPherson
    TI__Mastermind 32160 points

    Hi Mochizuki,

    Can you try using the PLL in Master Mode? That figure indicates the GPIO clock output is only intended to be used in Master Mode. The GPIO Mux is autoset by Master Slave mode and may be trying to read the empty SCLK pin in your Test 1 Configuration. In Test 2 that same Mux now has a SCLK source to output. Considering how the entire block is intended to be used in Master Mode, I would advise sticking to that. Otherwise I didn't notice any issues in your register configs. 

    Best Regards,

    Jeff

  • 0 in reply to Jeff McPherson
    Genius 3935 points

    Hi Jeff,

    Oh! It will bring quite big impact for the clock tree in this product.

    In the system, audio data interface device could provide BCK and LRCK, that is why we should use ADC slave mode.

    If PCM186x cannot distribute PLLed SCK on slave mode, is there any other alternative ADC device which can support I2S slave mode with PLL and distribute SCK?   

    How is TLV320ADC5140?

     

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 32160 points

    Unfortunately that isn't a functionality I can find. Typically PLL clocks are calculated to drive a particular system, not to be output to another one. 

    Even in Master Mode you can set the ratios of BCLK and FCLK to match whatever configuration you need. It's slightly less convenient, but if the PLL out is critical, that's what you will have to do.

    As I understand you need the PLL Clock Out to drive a PCM DAC? The PCM DACs have PLLs as well and can calculate their own system with a shared MCLK between the two devices. That could keep both devices as slaves.

    Best Regards,

    Jeff

  • 0 in reply to Jeff McPherson
    Genius 3935 points

    Hi Jeff,

    It is good suggestion, we will try to apply PCM512x PLL DAC to create SCK from BCK in slave mode.

    Regards,

    Mochizuki