TAS5760M: Inquiry

Hi Luis,

Good Day. Please see below the response of our customer to your reply. Thank you very much.

I have another query, "Minimum MCLK is 128*Fs, 192,256,384,512*Fs also acceptable".
Do MCLK need to vary depends on Fs or we can provide fixed 12MHZ clk from crystal oscillator to MCLK ?
Is there relationship between MCLK, SCLK and LRCLK? How to achieve it?

Best Regards,

Ray Vincent

Hi Ray

    All the clock must meet the requirement in the datasheet. If your FS changes, other clock rate must also change. 

   Usually our customer will use SOC on their system to generate the correct clock, not using crystal oscillator directly.

Hi Shadow,

Good Day. Please see below the response of our customer to your reply. Thank you very much.

SCLK, LRCLK and Data are generated as the part of I2S signal from the SOM.

But MCLK need to be generated separately.

I have seen from the table 6 provided in the datasheet that MCLK is minimum 128 times of Sample Rate.

So how to design and generate MCLK in that case?

In our previous design with TAS5755 we used MCLK as same as SCLK.

Best Regards,

Ray Vincent

Hi Ray

This is Jesse in the same team with Shadow.

Please allow me answer customer question.

for customer want to use i2c, the software control mode has to be used.

You can refer the table 6 and 7 as shadow said.

About the MCLK, for they want to use  SCLK = 32 * fs(sampling rate) as they said before,

then fs(sample rete) will determine which mclk cannot be used.

if fs = 24khz, 128*fs not available..

if fs = 16khz, 128*fs, 192*fs not available.

if fs = 12khz, 128*fs, 192*fs，256*fs，384*fs no available.

if fs = 88.2khz or 96khz, Double-Speed Mode will be used. then only 128, 192, 256*fs are available.

Hope it can help you.

thanks.

Jesse

Hi Jesse,

Good Day. Please see below the response of our customer to your reply. Thank you very much.

To add up some clarity,
1) Fs = 44100HZ, bits = 32, stereo mode.
SCLK = 32 * 44100 = 1411200(1.411MHz)
MCLK = 128*44100 = 5644800(5.644MHz)

2) Fs = 48000Hz, bits = 32, stereo mode.
SCLK = 32 * 48000 = 1536000(1.536MHz)
MCLK = 128 * 48000 = 6144000(6.144MHz)

In both the cases, do we need to provide exact MCLK as mentioned above or we can provide any single higher frequency(12MHz) or do we have any threshold/buffer for that?

Best Regards,

Ray Vincent