TLV320DAC3100: TLV320DAC3100: Noise while playing audio through speaker

Hi Deeksha,

Can you confirm the input clock frequencies match the device internal clock tree settings? You can share scope captures of the MCLK, BCLK and WCLK going to the DAC, as well as register dump after device initialization.

If you're only hearing the noise when playing audio it could be due to an incorrect sampling rate configuration.
You may also share a scope capture of the output signals, using an LC or RC filter to reconstruct the PWM signal into analog so that we can better understand what the noise is like.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan, 

I had used driver mentioned in below link and can refer for clock frequencies. I had used same clock frequency 

https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/sound/soc/codecs/tlv320aic31xx.c

Device dump :

Page 0 :

root@iWave-G39H:~# i2cdump -f -y 1 0x18
[2022-04-28 13:08:37.989] No size specified (using byte-data access)
[2022-04-28 13:08:37.989] 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
[2022-04-28 13:08:37.989] 00: 00 00 01 66 00 91 04 00 00 00 00 81 81 00 80 80 ..?f.??....??.??
[2022-04-28 13:08:37.989] 10: 08 00 81 81 80 80 04 00 00 00 01 0c 00 00 81 00 ?.?????...??..?.
[2022-04-28 13:08:37.989] 20: 00 00 00 00 80 10 00 00 00 00 00 00 00 00 00 00 ....??..........
[2022-04-28 13:08:37.989] 30: 00 00 00 02 32 12 03 02 02 11 10 00 01 04 00 3c ...?2??????.??.<
[2022-04-28 13:08:37.990] 40: 0c 12 12 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3 ???.o8.....???~?
[2022-04-28 13:08:37.990] 50: 00 00 80 00 00 00 00 00 7f 00 00 00 00 00 00 00 ..?.....?.......
[2022-04-28 13:08:38.032] 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.033] 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.033] 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.033] 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.033] a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.033] b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.070] c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.070] d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.070] e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:08:38.070] f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

Page 1 :

i2cdump -f -y 1 0x18
[2022-04-28 13:24:02.430] No size specified (using byte-data access)
[2022-04-28 13:24:02.431] 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
[2022-04-28 13:24:02.431] 00: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ?...............
[2022-04-28 13:24:02.431] 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 14 ...............?
[2022-04-28 13:24:02.431] 20: 86 3e 00 44 7f 7f 8d 7f 02 02 0d 00 20 86 00 80 ?>.D???????. ?.?
[2022-04-28 13:24:02.431] 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.431] 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.431] 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.474] 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.474] 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.474] 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.474] 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.474] a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.474] b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.526] c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.526] d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.526] e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
[2022-04-28 13:24:02.526] f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................

Attached scope capture with BCLK, MCLK and WCLK

As I mentioned in previous query , I am able to hear audio in HeadPhone and Speaker after enabling externally using amixer command.

https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1069951/tlv320dac3100-unsupported-frequency-while-playing-audio/3963304#3963304

So while playing audio through speaker there is noise and through headphone it is proper.

Regards,

Deeksha

Hi Ivan,

Here I attached output signals of speaker 

Regards,

Deeksha

Hi Deeksha,

I'll review your inputs and provide further comments later today.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Deeksha,

Deeksha J said:

Here I attached output signals of speaker 

Other than some ringing on the waveform, this capture seem like the Class-D output. The PWM is expected as it would start modulating when audio is played. It should not be causing noise at the speaker by itself.
Is this the signal you mean by noise? Perhaps you can share a microphone recording while playing on the speaker to hear what it sounds like?

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan,

Here I attached the captured audio file from speaker.

Regards,

Deeksha

Hi Deeksha,

Thanks for the audio capture.
I'll have to rework one of our EVM as these are not designed to have an external I2S source, then I'll verify the clock settings.

I think you may have to increase the DOSR value and adjust the other clock settings accordingly. The theory I have right now is that there is some aliasing at higher frequencies that the Class-D modulator is coupling it to lower frequencies, reason for not having the same distortion on the Headphone driver which is all analog.

Due to other active projects at this moment I'll have to get back by the end of the week or early next week.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan ,

What are the other clock settings need to be adjusted and based on what calculation have to do it. Let me know.

Regards,

Deeksha

Deeksha,

The complete clock tree diagram is available in data sheet Figure 6-19: https://www.ti.com/lit/ds/symlink/tlv320dac3100.pdf#page=52

What I'd suggest is to increase DOSR in multiples of 8, at the same time you have to consider the different requirements exposed on the following data sheet sections:

• 6.3.10.14 DAC Setup
• 6.3.11 CLOCK Generation and PLL
• 6.3.11.1 PLL

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan,

I had put up clock frequencies used in tlv320aic31xx.c driver. Here we are using 26MHz external clock so I had added below mclk/p =13000000 for all clk rate.

Any suggestions/observations on this

/* ADC dividers can be disabled by configuring them to 0 */
static const struct aic31xx_rate_divs aic31xx_divs[] = {
/* mclk/p rate pll: r j d dosr ndac mdac aors nadc madc */
/* 8k rate */
{ 512000, 8000, 4, 48, 0, 128, 48, 2, 128, 48, 2},
{12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
{12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},
{12500000, 8000, 1, 7, 8643, 128, 48, 2, 128, 48, 2},
{13000000, 8000, 1, 6, 3803, 128, 3, 27, 128, 3, 27},
/* 11.025k rate */
{ 705600, 11025, 3, 48, 0, 128, 24, 3, 128, 24, 3},
{12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
{12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},
{12500000, 11025, 1, 7, 2253, 128, 32, 2, 128, 32, 2},
{13000000, 11025, 1, 6, 1876, 128, 3, 19, 128, 3, 19},
/* 16k rate */
{ 512000, 16000, 4, 48, 0, 128, 16, 3, 128, 16, 3},
{ 1024000, 16000, 2, 48, 0, 128, 16, 3, 128, 16, 3},
{12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
{12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},
{12500000, 16000, 1, 7, 8643, 128, 24, 2, 128, 24, 2},
{13000000, 16000, 1, 6, 6166, 128, 3, 14, 128, 3, 14},
/* 22.05k rate */
{ 705600, 22050, 4, 36, 0, 128, 12, 3, 128, 12, 3},
{ 1411200, 22050, 2, 36, 0, 128, 12, 3, 128, 12, 3},
{12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
{12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},
{12500000, 22050, 1, 7, 2253, 128, 16, 2, 128, 16, 2},
{13000000, 22050, 1, 6, 5132, 128, 3, 10, 128, 3, 10},
/* 32k rate */
{ 1024000, 32000, 2, 48, 0, 128, 12, 2, 128, 12, 2},
{ 2048000, 32000, 1, 48, 0, 128, 12, 2, 128, 12, 2},
{12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
{12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},
{12500000, 32000, 1, 7, 8643, 128, 12, 2, 128, 12, 2},
{13000000, 32000, 1, 6, 6166, 128, 3, 7, 128, 3, 7},
/* 44.1k rate */
{ 1411200, 44100, 2, 32, 0, 128, 8, 2, 128, 8, 2},
{ 2822400, 44100, 1, 32, 0, 128, 8, 2, 128, 8, 2},
{12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
{12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},
{12500000, 44100, 1, 7, 2253, 128, 8, 2, 128, 8, 2},
{13000000, 44100, 1, 6, 5132, 128, 3, 5, 128, 3, 5},
/* 48k rate */
{ 1536000, 48000, 2, 32, 0, 128, 8, 2, 128, 8, 2},
{ 3072000, 48000, 1, 32, 0, 128, 8, 2, 128, 8, 2},
{12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
{12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4},
{12500000, 48000, 1, 7, 8643, 128, 8, 2, 128, 8, 2},
{13000000, 48000, 1, 6, 6166, 128, 7, 2, 128, 7, 2},
/* 88.2k rate */
{ 2822400, 88200, 2, 16, 0, 64, 8, 2, 64, 8, 2},
{ 5644800, 88200, 1, 16, 0, 64, 8, 2, 64, 8, 2},
{12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
{12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3},
{12500000, 88200, 1, 7, 2253, 64, 8, 2, 64, 8, 2},
{13000000, 88200, 1, 7, 2253, 64, 8, 2, 64, 8, 2},
/* 96k rate */
{ 3072000, 96000, 2, 16, 0, 64, 8, 2, 64, 8, 2},
{ 6144000, 96000, 1, 16, 0, 64, 8, 2, 64, 8, 2},
{12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
{12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4},
{12500000, 96000, 1, 7, 8643, 64, 8, 2, 64, 8, 2},
{13000000, 96000, 1, 6, 6166, 64, 7, 2, 64, 7, 2},
/* 176.4k rate */
{ 5644800, 176400, 2, 8, 0, 32, 8, 2, 32, 8, 2},
{11289600, 176400, 1, 8, 0, 32, 8, 2, 32, 8, 2},
{12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
{12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3},
{12500000, 176400, 1, 7, 2253, 32, 8, 2, 32, 8, 2},
{13000000, 176400, 1, 7, 2253, 32, 8, 2, 32, 8, 2},
/* 192k rate */
{ 6144000, 192000, 2, 8, 0, 32, 8, 2, 32, 8, 2},
{12288000, 192000, 1, 8, 0, 32, 8, 2, 32, 8, 2},
{12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
{12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4},
{12500000, 192000, 1, 7, 8643, 32, 8, 2, 32, 8, 2},
{13000000, 192000, 1, 6, 6166, 32, 7, 2, 32, 7, 2},
}; 

Regards,

Deeksha

Deeksha,

I assume you're having the same noise problem for all these different clock settings?
Haven't got time to complete the hardware test setup on my side yet.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan,

Yes I am getting noise for all  different clock settings. By when you can test at your end. Can you test at your end asap Since we have some urgency to resolve this at our side.

I had tested with these clock rate's - 8Hz, 44Hz, 48Hz

Regards,

Deeksha  

Hi Deeksha,

I've been testing some of these sampling rates and they seem to work OK on my side.
There are a few things I'd like to double check:

• Is your MCLK 26MHz for all cases?
• When you say you test 8kHz, 44kHz and 48kHz, you mean these are the WLCK frequencies coming from the host to TLV320DAC3100?
• Or your WCLK is always the same as well, but you only change the clock settings on TLV320DAC3100 regardless of the clock frequency coming into the device.

I'll share a report later this week with some captures of the input clocks and register dump for the clock settings.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan ,

-> Yes,  MCLK is given externally through  crystal.

-> Yes these are WCLK frequency this varies based on the audio file frequency which I play.

For example, if I play audio file with 8Khz , wclk is 8Khz  and if I play audio file with 48Khz ,wclk is 48Khz. 

tlv320aic31xx.c driver file takes MCLK/2 as 13000000 and rate value based on the audio[8khz/48KHz] which I play 

root@..:~# aplay -D plughw:1,0 /unit_tests/Audio/sample_22_frames.mp3
Playing raw data '/unit_tests/Audio/sample_22_frames.mp3' : Unsigned 8 bit, Rate 8000 Hz, Mono

-> May I know whether you had used any RC filter circuit , if so can you share snap of the filter design.

-> Which speaker have you used, Can you share the specification of speaker 

Here I attached link of speaker with which I have tested.

-> Here I attached our Schematics snip

Any suggestion on above.

Regards,

Deeksha 

Deeksha,

I'm using an AUX-0025 filter, but you can refer to this RC filter as well: https://www.ti.com/lit/an/sloa107/sloa107.pdf

For the speaker, I'm actually using a resistive load in series with an inductor, being 4Ohm+15uH.

During my tests, MCLK and I2S signals are synced, what I'll try next is using a separate MCLK source. I'll also review the schematic.

Best regards,
-Ivan Salazar
Applications Engineer