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PCM6360-Q1: Problem on data readback

Johnny Guo
Expert 4910 points

Part Number: PCM6360-Q1

Hi, team,

Some questions about PCM6360-Q1 in customer project.

Below is connection diagram. SOC TDM2 is CLK master, other devices are slave, including SOC TDM4 and ADC PCM6360-Q1.

When SOC TDM2 is master and SOC TDM4 port is slave, TDM format is shown below, TDM8.

ADC CLK，ADC is slave, TDM format is shown below, TDM8.

If PCM6360-Q1 config is the same, there will be three condition happening.

  1. Working in normal.
  2. All slot audio data is >6dB when ADSP readback ADC data with one bit backwards.
  3. Some of audio slot only show half part and <3dB when ADSP samping one bit ahead

Another two information.

  1. It is normal in all condition if readback with TDM4 another data line.
  2. If setting TDM4 to master, there will be no issue, but it cannot be like this due to system's limitation.

Questions:

  1. Can you provide some idea on this problem?
  2. Please check if some issue in below config on PCM6360-Q1.

address

default

value

 

0x00

0x00

0x00

set page 0

0x02

0x00

0x01

set not in sleep mode

0x07

0x30

0x34

set TDM mode, 32bit, FSYNC default, BCLK invert

0x0B

0x00

0x03

ch1 to TDM slot3

0x0C

0x01

0x04

ch2 to TDM slot4

0x0E

0x03

0x01

ch4 to TDM slot1

0x0F

0x04

0x00

ch5 to TDM slot0

0x21

0x22

0xA2

set gpio1 as MCLK and drive active low and weak high

0x4B

0x10

0x30

ch4 analog single-ended input, AC coupled input

0x50

0x10

0x30

ch5 analog single-ended input, AC coupled input

0x74

0x00

0xF8

ch1~ch5 output slot enable

0x75

0x00

0xF8

power up micbias, power up adc, power up pll, chn1~chn4 dynamic mode maximum

0x3B

0xD0

0xF0

Microphone bias is set to 9 V

0x3E

0xC9

0xC3

ch1 digital gain -3dB

0x43

0xC9

0xC3

ch2 digital gain -3dB

0x64

0x00

0xC2

ch1, chn2 diag enable, INxM pins of single-ended channels are included for diagnosis

0x65

0x37

0x22

INxP and INxM terminal short detect threshold value is 60 mV (typ), Short to VBAT_IN detect threshold value is 60 mV (typ)

0x66

0x87

0x2F

Short to ground detect threshold value is 120 mV (typ), Short to MICBIAS detect threshold value is 450 mV (typ)

0x67

0xB8

0x84

Fault monitoring repetition rate of 1 ms, 8 counts for debounce to filter-out any false faults detection

Thanks.

Johnny

  • 0
    TI__Guru 51200 points

    Hi Johnny,

    Can you clarify your three conditions? Are these conditions are you putting the device in? Or are these 3 different results with the same input? What's the difference between them?

    Also what is meant by "It is normal in all condition if readback with TDM4 another data line." Do you mean if you measure in parallel the ADC works fine, or is it that the data is correct but the ADC is wrong?

    Lastly, what frequencies are marked on the diagram?

    Best regards,

    Jeff

  • 0
    Prodigy 20 points

    Hi, Jeff,

    Can you clarify your three conditions? Are these conditions are you putting the device in? Or are these 3 different results with the same input? What's the difference between them?

    The three conditions happened in different power up time.

    Also what is meant by "It is normal in all condition if readback with TDM4 another data line." Do you mean if you measure in parallel the ADC works fine, or is it that the data is correct but the ADC is wrong?

    There are 2 SDIN line in TDM4, SDIN1 line is connected with ADC, SDIN2 line is connected with TDM2 SDOUT. TDM2 is the master of BLCK and FSYNC. We can dump audio stream data from the 2 SDIN line in TDM4. The data from SDIN2 is always ok.

    Lastly, what frequencies are marked on the diagram?

    The FSYNC is 48kHz, the BLCK is 12.288MHz.

    We need you to confirm if the register config is right or not. Do you have any advice for this situation?

  • 0 in reply to Yi Wang
    TI__Guru 51200 points

    Hi Yi,

    Your register settings appear correct to me. Since this issue appears related to power up, I would first isolate the ADC from the circuit and make sure it is consistently working at start up. I also notice that BCLK has a termination resistor but LRCLK does not. Make sure the clocks that are coming to the ADC are clean. 

    I am also confused on how you are getting TDM8 when the receiver is TDM4?

    Thank you,

    Jeff 

  • 0 in reply to Yi Wang
    TI__Expert 4910 points

    Hi Jeff,

    According to customer's reply, can you help confirm if there is some problem in ADC config?

    Thanks.

    Johnny

  • 0 in reply to Johnny Guo
    TI__Guru 51200 points

    Hi Johnny,

    See my above reply

  • 0 in reply to Jeff McPherson
    Prodigy 20 points

    Hi Jeff,

    Jeff McPherson said:
    . I also notice that BCLK has a termination resistor but LRCLK does not. Make sure the clocks that are coming to the ADC are clean. 

    It is true, our EE team has notice this difference and will move out the resistor to check if it will get better.

    Yellow is LRCLK, Green is BCLK, blue is data line. It seems follow the spec.

    Jeff McPherson said:
    I am also confused on how you are getting TDM8 when the receiver is TDM4?

    The TDM4 and TDM2 are in Qcom6155, we config the TDM2 as CLK master, TDM4 as CLK slave. We can dump data in Qcom ADSP.

  • 0 in reply to Yi Wang
    TI__Guru 51200 points

    Hi Yi,

    Yes I agree the clock seems okay. Your errors seem to be more of an issue with the system decoding rather than the ADC encoding, especially since the device sometimes works without changing any registers. I doubt this is a register issue. Unfortunately I can't support debugging a Qualcomm device.

    Best regards,

    Jeff