Hi team,
I have a question about the serial audio output format of this device.
I plan to use it as slave mode.
1. Does this device operate without MCLK input? BCLK and FSYNC only supplied from SoC.
ex... CLK_SRC register setting DIS_PLL_SLV_CLK_SRC [b7] = 0d (BCLK is used as the audio root clock source)
2. For Figure 24. TDM Mode Standard Protocol Timing (TX_OFFSET=0) figure, FSYNC duration seems minimum 1 BCLK pulse.
In TDM mode, is there minimum and maximum duration of FSYNC pulse?
As far as it drops to Low before the next FSYNC cycle, the duration of FSYNC High pulse doesn't care?
regards,
